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up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address

main
Istvan Csomortani 2015-09-29 14:19:52 +03:00
parent a0ac0e912b
commit cffb2e6226
3 changed files with 10 additions and 12 deletions
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3
library/common/ad_gt_common_1.v
View File

@ -188,8 +188,7 @@ module ad_gt_common_1 (
.up_drp_ready (up_drp_qpll1_ready_s));
up_gt #(
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.ID (ID))
.GTH_OR_GTX_N (GTH_OR_GTX_N))
i_up (
.up_drp_qpll0_sel (up_drp_qpll0_sel_s),
.up_drp_qpll0_wr (up_drp_qpll0_wr_s),

10
library/common/up_gt.v
View File

@ -69,9 +69,7 @@ module up_gt (
// parameters
localparam [31:0] VERSION = 32'h00070161;
parameter integer GTH_OR_GTX_N = 0;
parameter integer ID = 0;
// drp interface
@ -104,7 +102,6 @@ module up_gt (
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_drp_qpll0_sel = 'd0;
reg up_drp_qpll0_wr = 'd0;
reg up_drp_qpll0_status = 'd0;
@ -137,7 +134,6 @@ module up_gt (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_drp_qpll0_sel <= 'd0;
up_drp_qpll0_wr <= 'd0;
up_drp_qpll0_status <= 'd0;
@ -154,9 +150,6 @@ module up_gt (
up_drp_qpll1_rdata_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_drp_qpll0_sel <= 1'b1;
up_drp_qpll0_wr <= ~up_wdata[28];
@ -210,9 +203,6 @@ module up_gt (
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h14: up_rdata <= {3'd0, up_drp_qpll0_rwn,
up_drp_qpll0_addr, up_drp_qpll0_wdata};
8'h15: up_rdata <= {15'd0, up_drp_qpll0_status, up_drp_qpll0_rdata};

9
library/common/up_gt_channel.v
View File

@ -143,6 +143,7 @@ module up_gt_channel (
// parameters
localparam [31:0] VERSION = 32'h00070161;
parameter integer ID = 0;
parameter integer GTH_OR_GTX_N = 0;
@ -354,6 +355,7 @@ module up_gt_channel (
reg tx_up_sync_m1 = 'd0;
reg tx_up_sync = 'd0;
reg tx_ip_sync = 'd0;
reg [31:0] up_scratch = 'd0;
// internal signals
@ -407,6 +409,7 @@ module up_gt_channel (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_lpm_dfe_n <= 'd0;
up_cpll_pd <= 'd1;
up_drp_resetn <= 'd0;
@ -461,6 +464,9 @@ module up_gt_channel (
up_es_dma_err_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin
up_lpm_dfe_n <= up_wdata[1];
up_cpll_pd <= up_wdata[0];
@ -605,6 +611,9 @@ module up_gt_channel (
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h04: up_rdata <= {30'd0, up_lpm_dfe_n, up_cpll_pd};
8'h05: up_rdata <= {30'd0, up_drp_resetn, up_pll_resetn};
8'h08: up_rdata <= {31'd0, up_rx_gt_resetn};