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a10gx- change ddr to 1G

main
Rejeesh Kutty 2017-05-15 09:32:36 -04:00
parent 63b701ccab
commit cfcb269d38
2 changed files with 37 additions and 21 deletions
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14
projects/common/a10gx/a10gx_system_qsys.tcl
View File

@ -45,7 +45,7 @@ add_connection sys_clk.clk_reset sys_tlb_mem.reset2
add_instance sys_ddr3_cntrl altera_emif
set_instance_parameter_value sys_ddr3_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR3}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_MEM_CLK_FREQ_MHZ} {533.333}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_MEM_CLK_FREQ_MHZ} {1066.667}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {0}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {133.333}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_IO} {0}
@ -56,7 +56,7 @@ set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_CK_MODE_ENUM} {CURREN
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IO_STD_ENUM} {IO_STD_SSTL_15}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_15}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {IN_OCT_40_CAL}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {IN_OCT_120_CAL}
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_LVDS}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DQ_WIDTH} {64}
@ -64,11 +64,11 @@ set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_ROW_ADDR_WIDTH} {12}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_COL_ADDR_WIDTH} {10}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_BANK_ADDR_WIDTH} {3}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DM_EN} {1}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TCL} {13}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_WTCL} {9}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {10.285}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {10.285}
set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {4.0}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TCL} {14}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_WTCL} {10}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {13.09}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {13.09}
set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {5.0}
set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1}
add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n
add_interface sys_ddr3_cntrl_mem conduit end

44
projects/daq2/a10gx/system_constr.sdc
View File

@ -14,30 +14,46 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \
i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}]
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-to [get_clocks {i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-through [get_nets *altera_jesd204_tx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-through [get_nets *altera_jesd204_tx_ctl_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_csr_inst*] \
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_ctl_inst*] \
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_0|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_1|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_2|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_3|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]