diff --git a/library/util_axis_fifo/address_gray.v b/library/util_axis_fifo/address_gray.v
index a6aad02e3..a75d3368d 100644
--- a/library/util_axis_fifo/address_gray.v
+++ b/library/util_axis_fifo/address_gray.v
@@ -41,7 +41,6 @@ module fifo_address_gray (
 	input m_axis_aresetn,
 	input m_axis_ready,
 	output reg m_axis_valid,
-	output [ADDRESS_WIDTH-1:0] m_axis_raddr_next,
 	output reg [ADDRESS_WIDTH:0] m_axis_level,
 
 	input s_axis_aclk,
@@ -70,7 +69,6 @@ wire [ADDRESS_WIDTH:0] m_axis_raddr_gray_next;
 wire [ADDRESS_WIDTH:0] m_axis_waddr_gray;
 
 assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
-assign m_axis_raddr_next = _m_axis_raddr_next[ADDRESS_WIDTH-1:0];
 
 always @(*)
 begin
diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v
index fb56c1ed6..5541091c0 100644
--- a/library/util_axis_fifo/address_gray_pipelined.v
+++ b/library/util_axis_fifo/address_gray_pipelined.v
@@ -41,7 +41,6 @@ module fifo_address_gray_pipelined (
 	input m_axis_aresetn,
 	input m_axis_ready,
 	output reg m_axis_valid,
-	output [ADDRESS_WIDTH-1:0] m_axis_raddr_next,
 	output [ADDRESS_WIDTH-1:0] m_axis_raddr,
 	output reg [ADDRESS_WIDTH:0] m_axis_level,
 
@@ -65,7 +64,6 @@ reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
 wire [ADDRESS_WIDTH:0] _m_axis_waddr;
 
 assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
-assign m_axis_raddr_next = _m_axis_raddr_next[ADDRESS_WIDTH-1:0];
 assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
 
 always @(*)
diff --git a/library/util_axis_fifo/address_sync.v b/library/util_axis_fifo/address_sync.v
index e1594efc1..7b02b6e13 100644
--- a/library/util_axis_fifo/address_sync.v
+++ b/library/util_axis_fifo/address_sync.v
@@ -43,7 +43,6 @@ module fifo_address_sync (
 	input m_axis_ready,
 	output reg m_axis_valid,
 	output reg  [ADDRESS_WIDTH-1:0] m_axis_raddr,
-	output reg [ADDRESS_WIDTH-1:0] m_axis_raddr_next,
 	output [ADDRESS_WIDTH:0] m_axis_level,
 
 	output reg s_axis_ready,
@@ -65,14 +64,6 @@ assign m_axis_level = level;
 wire read = m_axis_ready & m_axis_valid;
 wire write = s_axis_ready & s_axis_valid;
 
-always @(*)
-begin
-	if (read)
-		m_axis_raddr_next <= m_axis_raddr + 1'b1;
-	else
-		m_axis_raddr_next <= m_axis_raddr;
-end
-
 always @(posedge clk)
 begin
 	if (resetn == 1'b0) begin
@@ -81,7 +72,8 @@ begin
 	end else begin
 		if (write)
 			s_axis_waddr <= s_axis_waddr + 1'b1;
-		m_axis_raddr <= m_axis_raddr_next;
+		if (read)
+			m_axis_raddr <= m_axis_raddr + 1'b1;
 	end
 end