zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad_*_clk: altera-pll not supported by qsys flow

main
Rejeesh Kutty 2016-05-16 12:16:41 -04:00
parent 4fbff45e27
commit cd7c9c99ed
2 changed files with 42 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
library/common/altera/ad_cmos_clk.v
View File

@ -46,8 +46,6 @@ module ad_cmos_clk (
clk);
parameter DEVICE_TYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
input rst;
output locked;
@ -57,11 +55,33 @@ module ad_cmos_clk (
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_clk i_clk (
.rst (rst),
.refclk (clk_in),
.outclk_0 (clk),
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("source synchronous"),
.number_of_clocks(1),
.output_clock_frequency0("0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in),
.outclk (clk),
.fboutclk (),
.fbclk (1'b0),
.locked (locked));
end
endgenerate
endmodule

20
library/common/altera/ad_lvds_clk.v
View File

@ -57,11 +57,31 @@ module ad_lvds_clk (
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_clk i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk_0 (clk),
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("lvds"),
.number_of_clocks(1),
.output_clock_frequency0("250.0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk (clk),
.locked (locked));
end
endgenerate
endmodule