From cd163e36c7e512a4e4045f1fc41d3d67b3f3b082 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 20 Jun 2018 17:35:18 +0300 Subject: [PATCH] axi_adrv9009: Added option for second observation channel --- library/axi_adrv9009/axi_adrv9009.v | 16 ++- library/axi_adrv9009/axi_adrv9009_hw.tcl | 16 +++ library/axi_adrv9009/axi_adrv9009_if.v | 110 +++++++++++------- .../axi_adrv9009/axi_adrv9009_rx_channel.v | 10 +- library/axi_adrv9009/axi_adrv9009_rx_os.v | 93 +++++++++++++-- 5 files changed, 186 insertions(+), 59 deletions(-) diff --git a/library/axi_adrv9009/axi_adrv9009.v b/library/axi_adrv9009/axi_adrv9009.v index 2ff46070a..c739fedb5 100644 --- a/library/axi_adrv9009/axi_adrv9009.v +++ b/library/axi_adrv9009/axi_adrv9009.v @@ -88,6 +88,12 @@ module axi_adrv9009 #( output adc_os_enable_q0, output adc_os_valid_q0, output [ 31:0] adc_os_data_q0, + output adc_os_enable_i1, + output adc_os_valid_i1, + output [ 31:0] adc_os_data_i1, + output adc_os_enable_q1, + output adc_os_valid_q1, + output [ 31:0] adc_os_data_q1, input adc_os_dovf, output dac_enable_i0, @@ -143,7 +149,7 @@ module axi_adrv9009 #( wire adc_os_rst; wire [ 63:0] adc_data_s; wire adc_os_valid_s; - wire [ 63:0] adc_os_data_s; + wire [127:0] adc_os_data_s; wire dac_rst; wire [127:0] dac_data_s; wire up_wreq_s; @@ -189,6 +195,7 @@ module axi_adrv9009 #( .adc_os_clk (adc_os_clk), .adc_rx_os_sof (adc_rx_os_sof), .adc_rx_os_data (adc_rx_os_data), + .adc_r1_mode (adc_r1_mode), .adc_data (adc_data_s), .adc_os_valid (adc_os_valid_s), .adc_os_data (adc_os_data_s), @@ -239,12 +246,19 @@ module axi_adrv9009 #( .adc_os_clk (adc_os_clk), .adc_os_valid (adc_os_valid_s), .adc_os_data (adc_os_data_s), + .adc_r1_mode (adc_r1_mode), .adc_os_enable_i0 (adc_os_enable_i0), .adc_os_valid_i0 (adc_os_valid_i0), .adc_os_data_i0 (adc_os_data_i0), .adc_os_enable_q0 (adc_os_enable_q0), .adc_os_valid_q0 (adc_os_valid_q0), .adc_os_data_q0 (adc_os_data_q0), + .adc_os_enable_i1 (adc_os_enable_i1), + .adc_os_valid_i1 (adc_os_valid_i1), + .adc_os_data_i1 (adc_os_data_i1), + .adc_os_enable_q1 (adc_os_enable_q1), + .adc_os_valid_q1 (adc_os_valid_q1), + .adc_os_data_q1 (adc_os_data_q1), .adc_os_dovf (adc_os_dovf), .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_adrv9009/axi_adrv9009_hw.tcl b/library/axi_adrv9009/axi_adrv9009_hw.tcl index 5fce47be0..a699c33ef 100644 --- a/library/axi_adrv9009/axi_adrv9009_hw.tcl +++ b/library/axi_adrv9009/axi_adrv9009_hw.tcl @@ -157,6 +157,22 @@ add_interface_port adc_os_ch_1 adc_os_data_q0 data Output 32 set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk set_interface_property adc_os_ch_1 associatedReset none +add_interface adc_os_ch_2 conduit end +add_interface_port adc_os_ch_2 adc_os_enable_i1 enable Output 1 +add_interface_port adc_os_ch_2 adc_os_valid_i1 valid Output 1 +add_interface_port adc_os_ch_2 adc_os_data_i1 data Output 32 + +set_interface_property adc_os_ch_2 associatedClock if_adc_os_clk +set_interface_property adc_os_ch_2 associatedReset none + +add_interface adc_os_ch_3 conduit end +add_interface_port adc_os_ch_3 adc_os_enable_q1 enable Output 1 +add_interface_port adc_os_ch_3 adc_os_valid_q1 valid Output 1 +add_interface_port adc_os_ch_3 adc_os_data_q1 data Output 32 + +set_interface_property adc_os_ch_3 associatedClock if_adc_os_clk +set_interface_property adc_os_ch_3 associatedReset none + ad_alt_intf signal adc_os_dovf input 1 ovf # dac-channel interface diff --git a/library/axi_adrv9009/axi_adrv9009_if.v b/library/axi_adrv9009/axi_adrv9009_if.v index e43d12d61..b9fffc0b8 100644 --- a/library/axi_adrv9009/axi_adrv9009_if.v +++ b/library/axi_adrv9009/axi_adrv9009_if.v @@ -44,10 +44,11 @@ module axi_adrv9009_if ( input adc_os_clk, input [ 3:0] adc_rx_os_sof, input [ 63:0] adc_rx_os_data, + input adc_r1_mode, output [ 63:0] adc_data, - output adc_os_valid, - output [ 63:0] adc_os_data, + output reg adc_os_valid, + output reg [127:0] adc_os_data, // transmit @@ -61,47 +62,74 @@ module axi_adrv9009_if ( wire [ 63:0] adc_rx_data_s; wire [ 63:0] adc_rx_os_data_s; + wire rx_os_sof; // delineating - assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data_s[((8* 6)+7):(8* 6)]; - assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data_s[((8* 7)+7):(8* 7)]; - assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data_s[((8* 4)+7):(8* 4)]; - assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data_s[((8* 5)+7):(8* 5)]; - assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data_s[((8* 2)+7):(8* 2)]; - assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data_s[((8* 3)+7):(8* 3)]; - assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data_s[((8* 0)+7):(8* 0)]; - assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data_s[((8* 1)+7):(8* 1)]; + assign adc_data[8* 7+:8] = adc_rx_data_s[8* 6+:8]; + assign adc_data[8* 6+:8] = adc_rx_data_s[8* 7+:8]; + assign adc_data[8* 5+:8] = adc_rx_data_s[8* 4+:8]; + assign adc_data[8* 4+:8] = adc_rx_data_s[8* 5+:8]; + assign adc_data[8* 3+:8] = adc_rx_data_s[8* 2+:8]; + assign adc_data[8* 2+:8] = adc_rx_data_s[8* 3+:8]; + assign adc_data[8* 1+:8] = adc_rx_data_s[8* 0+:8]; + assign adc_data[8* 0+:8] = adc_rx_data_s[8* 1+:8]; - assign adc_os_valid = 'd1; - assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data_s[((8* 6)+7):(8* 6)]; - assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data_s[((8* 7)+7):(8* 7)]; - assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data_s[((8* 4)+7):(8* 4)]; - assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data_s[((8* 5)+7):(8* 5)]; - assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data_s[((8* 2)+7):(8* 2)]; - assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data_s[((8* 3)+7):(8* 3)]; - assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data_s[((8* 0)+7):(8* 0)]; - assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data_s[((8* 1)+7):(8* 1)]; - - assign dac_tx_data[((8*15)+7):(8*15)] = dac_data[((8*14)+7):(8*14)]; - assign dac_tx_data[((8*14)+7):(8*14)] = dac_data[((8*15)+7):(8*15)]; - assign dac_tx_data[((8*13)+7):(8*13)] = dac_data[((8*12)+7):(8*12)]; - assign dac_tx_data[((8*12)+7):(8*12)] = dac_data[((8*13)+7):(8*13)]; - assign dac_tx_data[((8*11)+7):(8*11)] = dac_data[((8*10)+7):(8*10)]; - assign dac_tx_data[((8*10)+7):(8*10)] = dac_data[((8*11)+7):(8*11)]; - assign dac_tx_data[((8* 9)+7):(8* 9)] = dac_data[((8* 8)+7):(8* 8)]; - assign dac_tx_data[((8* 8)+7):(8* 8)] = dac_data[((8* 9)+7):(8* 9)]; - assign dac_tx_data[((8* 7)+7):(8* 7)] = dac_data[((8* 6)+7):(8* 6)]; - assign dac_tx_data[((8* 6)+7):(8* 6)] = dac_data[((8* 7)+7):(8* 7)]; - assign dac_tx_data[((8* 5)+7):(8* 5)] = dac_data[((8* 4)+7):(8* 4)]; - assign dac_tx_data[((8* 4)+7):(8* 4)] = dac_data[((8* 5)+7):(8* 5)]; - assign dac_tx_data[((8* 3)+7):(8* 3)] = dac_data[((8* 2)+7):(8* 2)]; - assign dac_tx_data[((8* 2)+7):(8* 2)] = dac_data[((8* 3)+7):(8* 3)]; - assign dac_tx_data[((8* 1)+7):(8* 1)] = dac_data[((8* 0)+7):(8* 0)]; - assign dac_tx_data[((8* 0)+7):(8* 0)] = dac_data[((8* 1)+7):(8* 1)]; + assign dac_tx_data[8*15+:8] = dac_data[8*14+:8]; + assign dac_tx_data[8*14+:8] = dac_data[8*15+:8]; + assign dac_tx_data[8*13+:8] = dac_data[8*12+:8]; + assign dac_tx_data[8*12+:8] = dac_data[8*13+:8]; + assign dac_tx_data[8*11+:8] = dac_data[8*10+:8]; + assign dac_tx_data[8*10+:8] = dac_data[8*11+:8]; + assign dac_tx_data[8* 9+:8] = dac_data[8* 8+:8]; + assign dac_tx_data[8* 8+:8] = dac_data[8* 9+:8]; + assign dac_tx_data[8* 7+:8] = dac_data[8* 6+:8]; + assign dac_tx_data[8* 6+:8] = dac_data[8* 7+:8]; + assign dac_tx_data[8* 5+:8] = dac_data[8* 4+:8]; + assign dac_tx_data[8* 4+:8] = dac_data[8* 5+:8]; + assign dac_tx_data[8* 3+:8] = dac_data[8* 2+:8]; + assign dac_tx_data[8* 2+:8] = dac_data[8* 3+:8]; + assign dac_tx_data[8* 1+:8] = dac_data[8* 0+:8]; + assign dac_tx_data[8* 0+:8] = dac_data[8* 1+:8]; // instantiations + always @(posedge adc_clk) begin + if (adc_r1_mode == 1'b1) begin + adc_os_valid <= 'd1; + adc_os_data[8* 7+:8] <= adc_rx_os_data_s[8* 6+:8]; + adc_os_data[8* 6+:8] <= adc_rx_os_data_s[8* 7+:8]; + adc_os_data[8* 5+:8] <= adc_rx_os_data_s[8* 4+:8]; + adc_os_data[8* 4+:8] <= adc_rx_os_data_s[8* 5+:8]; + adc_os_data[8* 3+:8] <= adc_rx_os_data_s[8* 2+:8]; + adc_os_data[8* 2+:8] <= adc_rx_os_data_s[8* 3+:8]; + adc_os_data[8* 1+:8] <= adc_rx_os_data_s[8* 0+:8]; + adc_os_data[8* 0+:8] <= adc_rx_os_data_s[8* 1+:8]; + adc_os_data[127:64] <= 64'h0; + end else begin + adc_os_valid <= !adc_os_valid; + if (adc_os_valid == 1'b1) begin + adc_os_data[8*13+:8] <= adc_rx_os_data_s[8* 6+:8]; + adc_os_data[8*12+:8] <= adc_rx_os_data_s[8* 7+:8]; + adc_os_data[8* 9+:8] <= adc_rx_os_data_s[8* 4+:8]; + adc_os_data[8* 8+:8] <= adc_rx_os_data_s[8* 5+:8]; + adc_os_data[8* 5+:8] <= adc_rx_os_data_s[8* 2+:8]; + adc_os_data[8* 4+:8] <= adc_rx_os_data_s[8* 3+:8]; + adc_os_data[8* 1+:8] <= adc_rx_os_data_s[8* 0+:8]; + adc_os_data[8* 0+:8] <= adc_rx_os_data_s[8* 1+:8]; + end else begin + adc_os_data[8*15+:8] <= adc_rx_os_data_s[8* 6+:8]; + adc_os_data[8*14+:8] <= adc_rx_os_data_s[8* 7+:8]; + adc_os_data[8*11+:8] <= adc_rx_os_data_s[8* 4+:8]; + adc_os_data[8*10+:8] <= adc_rx_os_data_s[8* 5+:8]; + adc_os_data[8* 7+:8] <= adc_rx_os_data_s[8* 2+:8]; + adc_os_data[8* 6+:8] <= adc_rx_os_data_s[8* 3+:8]; + adc_os_data[8* 3+:8] <= adc_rx_os_data_s[8* 0+:8]; + adc_os_data[8* 2+:8] <= adc_rx_os_data_s[8* 1+:8]; + end + end + end + genvar n; generate @@ -110,16 +138,16 @@ module axi_adrv9009_if ( ad_xcvr_rx_if i_xcvr_rx_if ( .rx_clk (adc_clk), .rx_ip_sof (adc_rx_sof), - .rx_ip_data (adc_rx_data[((n*32)+31):(n*32)]), + .rx_ip_data (adc_rx_data[n*32+:32]), .rx_sof (), - .rx_data (adc_rx_data_s[((n*32)+31):(n*32)])); + .rx_data (adc_rx_data_s[n*32+:32])); ad_xcvr_rx_if i_xcvr_rx_os_if ( .rx_clk (adc_os_clk), .rx_ip_sof (adc_rx_os_sof), - .rx_ip_data (adc_rx_os_data[((n*32)+31):(n*32)]), - .rx_sof (), - .rx_data (adc_rx_os_data_s[((n*32)+31):(n*32)])); + .rx_ip_data (adc_rx_os_data[n*32+:32]), + .rx_sof (rx_os_sof), + .rx_data (adc_rx_os_data_s[n*32+:32])); end endgenerate diff --git a/library/axi_adrv9009/axi_adrv9009_rx_channel.v b/library/axi_adrv9009/axi_adrv9009_rx_channel.v index 7b7875bc1..2cf259c79 100644 --- a/library/axi_adrv9009/axi_adrv9009_rx_channel.v +++ b/library/axi_adrv9009/axi_adrv9009_rx_channel.v @@ -45,15 +45,15 @@ module axi_adrv9009_rx_channel #( // adc interface - input adc_clk, - input adc_rst, - input adc_valid_in, + input adc_clk, + input adc_rst, + input adc_valid_in, input [(DATA_WIDTH-1):0] adc_data_in, - output adc_valid_out, + output adc_valid_out, output [(DATA_WIDTH-1):0] adc_data_out, input [(DATA_WIDTH-1):0] adc_data_iq_in, output [(DATA_WIDTH-1):0] adc_data_iq_out, - output adc_enable, + output adc_enable, // channel interface diff --git a/library/axi_adrv9009/axi_adrv9009_rx_os.v b/library/axi_adrv9009/axi_adrv9009_rx_os.v index e2dc25f08..cd9ff1e01 100644 --- a/library/axi_adrv9009/axi_adrv9009_rx_os.v +++ b/library/axi_adrv9009/axi_adrv9009_rx_os.v @@ -45,7 +45,8 @@ module axi_adrv9009_rx_os #( output adc_os_rst, input adc_os_clk, input adc_os_valid, - input [ 63:0] adc_os_data, + input [127:0] adc_os_data, + output adc_r1_mode, // dma interface @@ -55,6 +56,12 @@ module axi_adrv9009_rx_os #( output adc_os_enable_q0, output adc_os_valid_q0, output [ 31:0] adc_os_data_q0, + output adc_os_enable_i1, + output adc_os_valid_i1, + output [ 31:0] adc_os_data_i1, + output adc_os_enable_q1, + output adc_os_valid_q1, + output [ 31:0] adc_os_data_q1, input adc_os_dovf, // processor interface @@ -81,12 +88,14 @@ module axi_adrv9009_rx_os #( wire [ 31:0] adc_os_data_iq_i0_s; wire [ 31:0] adc_os_data_iq_q0_s; - wire [ 1:0] up_adc_pn_err_s; - wire [ 1:0] up_adc_pn_oos_s; - wire [ 1:0] up_adc_or_s; - wire [ 2:0] up_wack_s; - wire [ 2:0] up_rack_s; - wire [ 31:0] up_rdata_s[0:2]; + wire [ 31:0] adc_os_data_iq_i1_s; + wire [ 31:0] adc_os_data_iq_q1_s; + wire [ 3:0] up_adc_pn_err_s; + wire [ 3:0] up_adc_pn_oos_s; + wire [ 3:0] up_adc_or_s; + wire [ 4:0] up_wack_s; + wire [ 4:0] up_rack_s; + wire [ 31:0] up_rdata_s[0:4]; // processor read interface @@ -104,7 +113,7 @@ module axi_adrv9009_rx_os #( up_status_or <= | up_adc_or_s; up_wack <= | up_wack_s; up_rack <= | up_rack_s; - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4] ; end end @@ -172,6 +181,66 @@ module axi_adrv9009_rx_os #( .up_rdata (up_rdata_s[1]), .up_rack (up_rack_s[1])); + axi_adrv9009_rx_channel #( + .Q_OR_I_N (2), + .COMMON_ID ('h21), + .CHANNEL_ID (2), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (32)) + i_rx_os_channel_2 ( + .adc_clk (adc_os_clk), + .adc_rst (adc_os_rst), + .adc_valid_in (adc_os_valid), + .adc_data_in (adc_os_data[95:64]), + .adc_valid_out (adc_os_valid_i1), + .adc_data_out (adc_os_data_i1), + .adc_data_iq_in (adc_os_data_iq_q1_s), + .adc_data_iq_out (adc_os_data_iq_i1_s), + .adc_enable (adc_os_enable_i1), + .up_adc_pn_err (up_adc_pn_err_s[2]), + .up_adc_pn_oos (up_adc_pn_oos_s[2]), + .up_adc_or (up_adc_or_s[2]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + axi_adrv9009_rx_channel #( + .Q_OR_I_N (3), + .COMMON_ID ('h21), + .CHANNEL_ID (3), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (32)) + i_rx_os_channel_3 ( + .adc_clk (adc_os_clk), + .adc_rst (adc_os_rst), + .adc_valid_in (adc_os_valid), + .adc_data_in (adc_os_data[127:96]), + .adc_valid_out (adc_os_valid_q1), + .adc_data_out (adc_os_data_q1), + .adc_data_iq_in (adc_os_data_iq_i1_s), + .adc_data_iq_out (adc_os_data_iq_q1_s), + .adc_enable (adc_os_enable_q1), + .up_adc_pn_err (up_adc_pn_err_s[3]), + .up_adc_pn_oos (up_adc_pn_oos_s[3]), + .up_adc_or (up_adc_or_s[3]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + // common processor control up_adc_common #( @@ -181,7 +250,7 @@ module axi_adrv9009_rx_os #( .mmcm_rst (), .adc_clk (adc_os_clk), .adc_rst (adc_os_rst), - .adc_r1_mode (), + .adc_r1_mode (adc_r1_mode), .adc_ddr_edgesel (), .adc_pin_mode (), .adc_status (1'b1), @@ -214,11 +283,11 @@ module axi_adrv9009_rx_os #( .up_wreq (up_wreq), .up_waddr (up_waddr), .up_wdata (up_wdata), - .up_wack (up_wack_s[2]), + .up_wack (up_wack_s[4]), .up_rreq (up_rreq), .up_raddr (up_raddr), - .up_rdata (up_rdata_s[2]), - .up_rack (up_rack_s[2])); + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); endmodule