diff --git a/library/axi_clkgen/axi_clkgen_constr.xdc b/library/axi_clkgen/axi_clkgen_constr.xdc
new file mode 100644
index 000000000..cc5766194
--- /dev/null
+++ b/library/axi_clkgen/axi_clkgen_constr.xdc
@@ -0,0 +1,46 @@
+set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
+set delay_clk [get_clocks -of_objects [get_ports drp_clk]]
+
+set_property ASYNC_REG TRUE \
+  [get_cells -hier *up_drp_locked_m1_reg*] \
+  [get_cells -hier *up_drp_locked_m2_reg*] \
+  [get_cells -hier *up_drp_ack_t_m1_reg*] \
+  [get_cells -hier *up_drp_ack_t_m2_reg*] \
+  [get_cells -hier *drp_sel_t_m1_reg*] \
+  [get_cells -hier *drp_sel_t_m2_reg*] \
+  [get_cells -hier *drp_locked_m1_reg*] \
+  [get_cells -hier *drp_locked_reg*]
+
+set_false_path \
+  -from [get_cells -hier up_drp_sel_t_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier drp_sel_t_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier up_drp_rwn_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier drp_wr_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $delay_clk]
+set_max_delay -datapath_only \
+  -from [get_cells -hier up_drp_addr_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier drp_addr_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $delay_clk]
+set_max_delay -datapath_only \
+  -from [get_cells -hier up_drp_wdata_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier drp_wdata_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $delay_clk]
+set_false_path \
+  -from [get_cells -hier drp_locked_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_drp_locked_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier drp_ack_t_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_drp_ack_t_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier drp_rdata_int_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_drp_rdata_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_max_delay -datapath_only \
+  -from [get_cells -hier drp_rdata_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier drp_rdata_int_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $delay_clk]
+
+set_false_path \
+  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
diff --git a/library/axi_clkgen/axi_clkgen_ip.tcl b/library/axi_clkgen/axi_clkgen_ip.tcl
index 7f0296682..36811ff7a 100644
--- a/library/axi_clkgen/axi_clkgen_ip.tcl
+++ b/library/axi_clkgen/axi_clkgen_ip.tcl
@@ -10,10 +10,14 @@ adi_ip_files axi_clkgen [list \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/up_drp_cntrl.v" \
   "$ad_hdl_dir/library/common/up_clkgen.v" \
+  "axi_clkgen_constr.xdc" \
   "axi_clkgen.v" ]
 
 adi_ip_properties axi_clkgen
 
+adi_ip_constraints axi_clkgen [list \
+  "axi_clkgen_constr.xdc" ]
+
 set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
   [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]