altera- java/tcl mess handling

main
Rejeesh Kutty 2016-10-31 10:54:07 -04:00
parent a9d03af771
commit cc75fa3dfe
5 changed files with 57 additions and 133 deletions

View File

@ -191,7 +191,7 @@ module __ad_serdes_clk__ #(
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int),
.pll_reconfig_address (up_drp_addr_int[5:0]),
.pll_reconfig_writedata (up_drp_wdata_int));
cyclonev_pll_lvds_output #(

View File

@ -136,89 +136,17 @@ module __ad_serdes_in__ #(
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
altlvds_rx #(
.buffer_implementation ("RAM"),
.cds_mode ("UNUSED"),
.common_rx_tx_pll ("ON"),
.data_align_rollover (4),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.dpa_initial_phase_value (0),
.dpll_lock_count (0),
.dpll_lock_window (0),
.enable_clock_pin_mode ("UNUSED"),
.enable_dpa_align_to_rising_edge_only ("OFF"),
.enable_dpa_calibration ("ON"),
.enable_dpa_fifo ("UNUSED"),
.enable_dpa_initial_phase_selection ("OFF"),
.enable_dpa_mode ("OFF"),
.enable_dpa_pll_calibration ("OFF"),
.enable_soft_cdr_mode ("OFF"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.input_data_rate (500),
.intended_device_family ("Cyclone V"),
.lose_lock_on_one_change ("UNUSED"),
.lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"),
.lpm_type ("altlvds_rx"),
.number_of_channels (DATA_WIDTH),
.outclock_resource ("Regional clock"),
.pll_operation_mode ("NORMAL"),
.pll_self_reset_on_loss_lock ("UNUSED"),
.port_rx_channel_data_align ("PORT_UNUSED"),
.port_rx_data_align ("PORT_UNUSED"),
.refclk_frequency ("250.000000 MHz"),
.registered_data_align_input ("UNUSED"),
.registered_output ("ON"),
.reset_fifo_at_first_lock ("UNUSED"),
.rx_align_data_reg ("RISING_EDGE"),
.sim_dpa_is_negative_ppm_drift ("OFF"),
.sim_dpa_net_ppm_variation (0),
.sim_dpa_output_clock_phase_shift (0),
.use_coreclock_input ("OFF"),
.use_dpll_rawperror ("OFF"),
.use_external_pll ("ON"),
.use_no_phase_shift ("ON"),
.x_on_bitslip ("ON"),
.clk_src_is_pll ("off"))
i_altlvds_rx (
.rx_inclock (clk),
.rx_in (data_in_p[n]),
.rx_outclock (),
.rx_out (data_out_s[n]),
.rx_locked (),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (~locked),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset ({7{1'b0}}),
.rx_channel_data_align ({7{1'b0}}),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset ({7{1'b0}}),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable ({7{1'b1}}),
.rx_dpll_hold ({7{1'b0}}),
.rx_dpll_reset ({7{1'b0}}),
.rx_enable (loaden),
.rx_fifo_reset ({7{1'b0}}),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset ({7{1'b0}}),
.rx_syncclock (1'b0));
assign delay_locked_s[n] = 1'b1;
ad_serdes_in_core_c5 #(
.SERDES_FACTOR (SERDES_FACTOR))
i_core (
.clk (clk),
.div_clk (div_clk),
.enable (loaden),
.data_in (data_in_p[n]),
.data (data_out_s[n]));
end
if (DEVICE_TYPE == ARRIA10) begin

View File

@ -109,53 +109,14 @@ module __ad_serdes_out__ #(
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
altlvds_tx #(
.center_align_msb ("UNUSED"),
.common_rx_tx_pll ("ON"),
.coreclock_divide_by (1),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.differential_drive (0),
.enable_clock_pin_mode ("UNUSED"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.intended_device_family ("Cyclone V"),
.lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"),
.lpm_type ("altlvds_tx"),
.multi_clock ("OFF"),
.number_of_channels (DATA_WIDTH),
.outclock_alignment ("EDGE_ALIGNED"),
.outclock_divide_by (2),
.outclock_duty_cycle (50),
.outclock_multiply_by (1),
.outclock_phase_shift (0),
.outclock_resource ("Regional clock"),
.output_data_rate (500),
.pll_compensation_mode ("AUTO"),
.pll_self_reset_on_loss_lock ("OFF"),
.preemphasis_setting (0),
.refclk_frequency ("250.000000 MHz"),
.registered_input ("TX_CORECLK"),
.use_external_pll ("ON"),
.use_no_phase_shift ("ON"),
.vod_setting (0),
.clk_src_is_pll ("off"))
i_altlvds_tx (
.tx_inclock (clk),
.tx_coreclock (div_clk),
.tx_in (data_in_s[n]),
.tx_outclock (),
.tx_out (data_out_p[n]),
.tx_locked (),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_data_reset (1'b0),
.tx_enable (loaden),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
ad_serdes_out_core_c5 #(
.SERDES_FACTOR (SERDES_FACTOR))
i_core (
.clk (clk),
.div_clk (div_clk),
.enable (loaden),
.data_out (data_out_p[n]),
.data (data_in_s[n]));
end
if (DEVICE_TYPE == ARRIA10) begin

View File

@ -436,8 +436,8 @@ module axi_ad9361_lvds_if #(
.data_in_p (rx_frame_in_p),
.data_in_n (rx_frame_in_n),
.up_clk (1'd0),
.up_dld (6'd0),
.up_dwdata (30'd0),
.up_dld (1'd0),
.up_dwdata (5'd0),
.up_drdata (),
.delay_clk (1'd0),
.delay_rst (1'd0),

View File

@ -89,6 +89,41 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } {
close $fp_target
}
proc ad_ip_parameter {pname ptype pdefault} {
add_parameter $pname $ptype $pdefault
set_parameter_property $pname HDL_PARAMETER true
set_parameter_property $pname ENABLED true
}
proc ad_ip_files {pname pfiles {pfunction ""}} {
set ftopfile [lindex $pfiles end]
set pfiles [lreplace $pfiles end end]
add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
set_fileset_property quartus_synth TOP_LEVEL $pname
foreach pfile $pfiles {
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile
}
set pfile $ftopfile
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
add_fileset quartus_sim SIM_VERILOG $pfunction ""
set_fileset_property quartus_sim TOP_LEVEL $pname
foreach pfile $pfiles {
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile
}
set pfile $ftopfile
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
}
proc ad_ip_intf_s_axi {aclk arstn} {
add_interface s_axi_clock clock end