wfifo: multi-channel option
Rejeesh Kutty
parent
2e877389b2
commit
cb0324c2b1
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@ -34,22 +34,8 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// allows conversions between the adc (or similar) interface to the dma (or similar).
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// * asymmetric bus widths in the range allowed by the fifo
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// * frequency -- dma can run slower at reduced channels
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// * drop or add channels -- post processing samples
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// * interface axis -- allows axi-stream interface
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//
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// allows conversions of clock/buswidth for adc/dac channels
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// in all cases bandwidth requirements must be met (read >= write).
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//
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// axis-interface support
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// * set DMA_READY_ENABLE parameter to 1.
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// * connect dma_wr as axis_valid, dma_wready as axis_ready
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// * make sure read bandwidth >= write bandwidth (or drop samples)
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// * some axis interface requires last (use a counter or such externally).
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//
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// the fifo is external- connect all the fifo_* signals to a fifo generator IP.
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// configure the IP to match the buswidths & clocks.
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// ***************************************************************************
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// ***************************************************************************
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@ -57,146 +43,327 @@
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module util_wfifo (
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// adc interface
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// d-in interface
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adc_rst,
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adc_clk,
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adc_wr,
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adc_wdata,
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adc_wovf,
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din_rst,
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din_clk,
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din_enable_0,
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din_valid_0,
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din_data_0,
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din_enable_1,
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din_valid_1,
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din_data_1,
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din_enable_2,
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din_valid_2,
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din_data_2,
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din_enable_3,
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din_valid_3,
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din_data_3,
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din_enable_4,
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din_valid_4,
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din_data_4,
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din_enable_5,
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din_valid_5,
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din_data_5,
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din_enable_6,
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din_valid_6,
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din_data_6,
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din_enable_7,
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din_valid_7,
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din_data_7,
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din_ovf,
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// dma interface
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// d-out interface
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dma_clk,
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dma_wr,
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dma_wdata,
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dma_wready,
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dma_wovf,
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// fifo interface
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fifo_rst,
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fifo_rstn,
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fifo_wr,
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fifo_wdata,
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fifo_wovf,
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fifo_rd,
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fifo_rdata,
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fifo_rempty);
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dout_rstn,
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dout_clk,
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dout_enable_0,
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dout_valid_0,
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dout_data_0,
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dout_enable_1,
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dout_valid_1,
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dout_data_1,
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dout_enable_2,
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dout_valid_2,
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dout_data_2,
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dout_enable_3,
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dout_valid_3,
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dout_data_3,
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dout_enable_4,
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dout_valid_4,
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dout_data_4,
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dout_enable_5,
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dout_valid_5,
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dout_data_5,
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dout_enable_6,
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dout_valid_6,
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dout_data_6,
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dout_enable_7,
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dout_valid_7,
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dout_data_7,
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dout_ovf);
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// parameters
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parameter ADC_DATA_WIDTH = 32;
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parameter DMA_DATA_WIDTH = 64;
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parameter DMA_READY_ENABLE = 0;
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// adc interface
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parameter NUM_OF_CHANNELS = 4;
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parameter DIN_DATA_WIDTH = 32;
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parameter DOUT_DATA_WIDTH = 64;
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parameter DIN_ADDR_WIDTH = 8;
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input adc_rst;
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input adc_clk;
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input adc_wr;
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input [ADC_DATA_WIDTH-1:0] adc_wdata;
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output adc_wovf;
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localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
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localparam ADDR_WIDTH = (DIN_ADDR_WIDTH > 4) ? DIN_ADDR_WIDTH : 4;
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localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;
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localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;
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localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;
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// dma interface
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// d-in interface
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input dma_clk;
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output dma_wr;
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output [DMA_DATA_WIDTH-1:0] dma_wdata;
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input dma_wready;
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input dma_wovf;
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input din_rst;
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input din_clk;
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input din_enable_0;
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input din_valid_0;
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input [DIN_DATA_WIDTH-1:0] din_data_0;
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input din_enable_1;
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input din_valid_1;
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input [DIN_DATA_WIDTH-1:0] din_data_1;
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input din_enable_2;
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input din_valid_2;
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input [DIN_DATA_WIDTH-1:0] din_data_2;
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input din_enable_3;
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input din_valid_3;
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input [DIN_DATA_WIDTH-1:0] din_data_3;
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input din_enable_4;
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input din_valid_4;
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input [DIN_DATA_WIDTH-1:0] din_data_4;
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input din_enable_5;
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input din_valid_5;
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input [DIN_DATA_WIDTH-1:0] din_data_5;
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input din_enable_6;
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input din_valid_6;
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input [DIN_DATA_WIDTH-1:0] din_data_6;
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input din_enable_7;
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input din_valid_7;
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input [DIN_DATA_WIDTH-1:0] din_data_7;
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output din_ovf;
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// fifo interface
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// dout interface
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output fifo_rst;
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output fifo_rstn;
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output fifo_wr;
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output [ADC_DATA_WIDTH-1:0] fifo_wdata;
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input fifo_wovf;
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output fifo_rd;
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input [DMA_DATA_WIDTH-1:0] fifo_rdata;
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input fifo_rempty;
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input dout_rstn;
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input dout_clk;
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output dout_enable_0;
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output dout_valid_0;
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output [DOUT_DATA_WIDTH-1:0] dout_data_0;
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output dout_enable_1;
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output dout_valid_1;
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output [DOUT_DATA_WIDTH-1:0] dout_data_1;
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output dout_enable_2;
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output dout_valid_2;
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output [DOUT_DATA_WIDTH-1:0] dout_data_2;
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output dout_enable_3;
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output dout_valid_3;
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output [DOUT_DATA_WIDTH-1:0] dout_data_3;
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output dout_enable_4;
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output dout_valid_4;
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output [DOUT_DATA_WIDTH-1:0] dout_data_4;
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output dout_enable_5;
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output dout_valid_5;
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output [DOUT_DATA_WIDTH-1:0] dout_data_5;
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output dout_enable_6;
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output dout_valid_6;
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output [DOUT_DATA_WIDTH-1:0] dout_data_6;
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output dout_enable_7;
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output dout_valid_7;
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output [DOUT_DATA_WIDTH-1:0] dout_data_7;
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input dout_ovf;
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// internal registers
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reg [ 1:0] adc_wovf_m = 'd0;
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reg adc_wovf = 'd0;
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reg dma_wr_int = 'd0;
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reg fifo_rst = 'd0;
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reg fifo_rst_p = 'd0;
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reg fifo_rstn = 'd0;
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reg [(DATA_WIDTH-1):0] din_wdata = 'd0;
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reg [ 7:0] din_enable = 'd0;
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reg [ 2:0] din_dcnt = 'd0;
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reg din_wr = 'd0;
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reg [(ADDR_WIDTH-1):0] din_waddr = 'd0;
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reg din_waddr_rel_t = 'd0;
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reg [(ADDR_WIDTH-1):0] din_waddr_rel = 'd0;
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reg [ 2:0] din_ovf_m = 'd0;
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reg din_ovf = 'd0;
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reg [ 2:0] dout_waddr_rel_t_m = 'd0;
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reg [(ADDR_WIDTH-1):0] dout_waddr_rel = 'd0;
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reg dout_ovf_int = 'd0;
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reg [ 7:0] dout_enable_m = 'd0;
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reg [ 7:0] dout_enable = 'd0;
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reg dout_rd = 'd0;
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reg dout_rd_d = 'd0;
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reg [(DATA_WIDTH-1):0] dout_rdata_d = 'd0;
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reg [(ADDR_WIDTH-1):0] dout_raddr = 'd0;
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// internal signals
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wire dma_wready_s;
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wire [DMA_DATA_WIDTH-1:0] dma_wdata_s;
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wire [ 7:0] din_enable_s;
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wire [ 7:0] din_valid_s;
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wire [(T_DIN_DATA_WIDTH-1):0] din_data_s;
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wire dout_waddr_rel_t_s;
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wire dout_rd_s;
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wire [(DATA_WIDTH-1):0] dout_rdata_s;
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wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s;
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// adc overflow
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// variables
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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adc_wovf_m <= 2'd0;
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adc_wovf <= 1'b0;
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end else begin
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adc_wovf_m[0] <= dma_wovf | fifo_wovf;
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adc_wovf_m[1] <= adc_wovf_m[0];
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adc_wovf <= adc_wovf_m[1];
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genvar n;
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// concat signals, valid_0 must always be active
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assign din_enable_s = { din_enable_7, din_enable_6, din_enable_5, din_enable_4,
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din_enable_3, din_enable_2, din_enable_1, din_enable_0};
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assign din_valid_s = { din_valid_7, din_valid_6, din_valid_5, din_valid_4,
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din_valid_3, din_valid_2, din_valid_1, din_valid_0};
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assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4,
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din_data_3, din_data_2, din_data_1, din_data_0};
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// dout_width >= din_width only
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generate
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for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
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if (M_MEM_RATIO == 1) begin
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always @(posedge din_clk) begin
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if (din_valid_s[n] == 1'b1) begin
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
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din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)];
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end
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end
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// write
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assign fifo_wr = adc_wr;
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genvar m;
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generate
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for (m = 0; m < ADC_DATA_WIDTH; m = m + 1) begin: g_wdata
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assign fifo_wdata[m] = adc_wdata[(ADC_DATA_WIDTH-1)-m];
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end else begin
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always @(posedge din_clk) begin
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if (din_valid_s[n] == 1'b1) begin
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
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{din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)],
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]};
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end
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end
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end
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end
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endgenerate
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// read
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assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
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assign fifo_rd = ~fifo_rempty & dma_wready_s;
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always @(posedge dma_clk) begin
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dma_wr_int <= fifo_rd;
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end
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genvar s;
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generate
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for (s = 0; s < DMA_DATA_WIDTH; s = s + 1) begin: g_rdata
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assign dma_wdata_s[s] = fifo_rdata[(DMA_DATA_WIDTH-1)-s];
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end
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endgenerate
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// reset & resetn
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always @(posedge dma_clk or posedge adc_rst) begin
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if (adc_rst == 1'b1) begin
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fifo_rst_p <= 1'd1;
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fifo_rst <= 1'd1;
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fifo_rstn <= 1'd0;
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always @(posedge din_clk) begin
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if (din_rst == 1'b1) begin
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din_enable <= 8'd0;
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din_dcnt <= 3'd0;
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din_wr <= 1'd0;
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din_waddr <= 5'd0;
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din_waddr_rel_t <= 1'd0;
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din_waddr_rel <= 5'd0;
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din_ovf_m <= 'd0;
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din_ovf <= 'd0;
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end else begin
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fifo_rst_p <= 1'b0;
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fifo_rst <= fifo_rst_p;
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fifo_rstn <= ~fifo_rst_p;
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din_enable <= din_enable_s;
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if (din_valid_s[0] == 1'b1) begin
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din_dcnt <= din_dcnt + 1'b1;
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end
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case (M_MEM_RATIO)
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8: din_wr <= din_valid_s[0] & din_dcnt[0] & din_dcnt[1] & din_dcnt[2];
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4: din_wr <= din_valid_s[0] & din_dcnt[0] & din_dcnt[1];
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2: din_wr <= din_valid_s[0] & din_dcnt[0];
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default: din_wr <= din_valid_s[0];
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endcase
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if (din_wr == 1'b1) begin
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din_waddr <= din_waddr + 1'b1;
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end
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if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd0)) begin
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din_waddr_rel_t <= ~din_waddr_rel_t;
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din_waddr_rel <= din_waddr;
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end
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din_ovf_m <= {din_ovf_m[1:0], dout_ovf_int};
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din_ovf <= din_ovf_m[2];
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end
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end
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// axis
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// read interface (bus expansion and/or clock conversion)
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ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
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.clk (dma_clk),
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.rst (fifo_rst),
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.valid (dma_wr_int),
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.last (1'd0),
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.data (dma_wdata_s),
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.inf_valid (dma_wr),
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.inf_last (),
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.inf_data (dma_wdata),
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.inf_ready (dma_wready_s));
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assign dout_waddr_rel_t_s = dout_waddr_rel_t_m[2] ^ dout_waddr_rel_t_m[1];
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always @(posedge dout_clk) begin
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if (dout_rstn == 1'b0) begin
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dout_waddr_rel_t_m <= 3'd0;
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dout_waddr_rel <= 'd0;
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dout_ovf_int <= 1'b1;
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end else begin
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dout_waddr_rel_t_m <= {dout_waddr_rel_t_m[1:0], din_waddr_rel_t};
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if (dout_waddr_rel_t_s == 1'b1) begin
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dout_waddr_rel <= din_waddr_rel;
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if (dout_raddr == dout_waddr_rel) begin
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dout_ovf_int <= dout_ovf;
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end else begin
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dout_ovf_int <= 1'b1;
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end
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end
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end
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end
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assign dout_rd_s = (dout_raddr == dout_waddr_rel) ? 1'b0 : 1'b1;
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assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
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assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata_d;
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always @(posedge dout_clk) begin
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if (dout_rstn == 1'b0) begin
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dout_enable_m <= 'd0;
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dout_enable <= 'd0;
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dout_rd <= 'd0;
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dout_rd_d <= 'd0;
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dout_rdata_d <= 'd0;
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dout_raddr <= 'd0;
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end else begin
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dout_enable_m <= din_enable;
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dout_enable <= dout_enable_m;
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dout_rd <= dout_rd_s;
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dout_rd_d <= dout_rd;
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dout_rdata_d <= dout_rdata_s;
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if (dout_rd_s == 1'b1) begin
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dout_raddr <= dout_raddr + 1'b1;
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end
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end
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end
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assign dout_enable_7 = dout_enable[7];
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assign dout_valid_7 = dout_rd_d;
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assign dout_data_7 = dout_data_s[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)];
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assign dout_enable_6 = dout_enable[6];
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assign dout_valid_6 = dout_rd_d;
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assign dout_data_6 = dout_data_s[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)];
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assign dout_enable_5 = dout_enable[5];
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assign dout_valid_5 = dout_rd_d;
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assign dout_data_5 = dout_data_s[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)];
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assign dout_enable_4 = dout_enable[4];
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assign dout_valid_4 = dout_rd_d;
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assign dout_data_4 = dout_data_s[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)];
|
||||
|
||||
assign dout_enable_3 = dout_enable[3];
|
||||
assign dout_valid_3 = dout_rd_d;
|
||||
assign dout_data_3 = dout_data_s[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)];
|
||||
|
||||
assign dout_enable_2 = dout_enable[2];
|
||||
assign dout_valid_2 = dout_rd_d;
|
||||
assign dout_data_2 = dout_data_s[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)];
|
||||
|
||||
assign dout_enable_1 = dout_enable[1];
|
||||
assign dout_valid_1 = dout_rd_d;
|
||||
assign dout_data_1 = dout_data_s[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)];
|
||||
|
||||
assign dout_enable_0 = dout_enable[0];
|
||||
assign dout_valid_0 = dout_rd_d;
|
||||
assign dout_data_0 = dout_data_s[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)];
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_mem #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
|
||||
.clka (din_clk),
|
||||
.wea (din_wr),
|
||||
.addra (din_waddr),
|
||||
.dina (din_wdata),
|
||||
.clkb (dout_clk),
|
||||
.addrb (dout_raddr),
|
||||
.doutb (dout_rdata_s));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,11 @@
|
|||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *adc_wovf_m*] \
|
||||
[get_cells -hier *fifo_rst_p*]
|
||||
|
||||
set_false_path \
|
||||
-to [get_cells -hier adc_wovf_m_reg[0]* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -from [get_cells -hier *dout_ovf_int* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *din_ovf_m* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -from [get_cells -hier *din_waddr_rel_t* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *dout_waddr_rel_t_m* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -from [get_cells -hier *din_enable* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *dout_enable_m* -filter {primitive_subgroup == flop}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hier */PRE -filter {NAME =~ *i_*fifo_rst*}]
|
||||
set_max_delay -datapath_only -from [get_cells -hier *din_waddr_rel* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *dout_waddr_rel* -filter {primitive_subgroup == flop}] 8
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hier */CLR -filter {NAME =~ *i_*fifo_rstn_reg*}]
|
||||
|
|
|
|||
|
|
@ -5,8 +5,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
|||
|
||||
adi_ip_create util_wfifo
|
||||
adi_ip_files util_wfifo [list \
|
||||
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
|
||||
"util_wfifo_constr.xdc" \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"util_wfifo.v" ]
|
||||
|
||||
adi_ip_properties_lite util_wfifo
|
||||
|
|
@ -15,6 +14,25 @@ adi_ip_constraints util_wfifo [list \
|
|||
"util_wfifo_constr.xdc" ]
|
||||
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
set_property driver_value 0 [ipx::get_ports *din_enable* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dout_ovf* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
|
||||
[ipx::get_ports *_1* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
|
||||
[ipx::get_ports *_2* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \
|
||||
[ipx::get_ports *_3* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \
|
||||
[ipx::get_ports *_4* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \
|
||||
[ipx::get_ports *_5* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \
|
||||
[ipx::get_ports *_6* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
|
||||
[ipx::get_ports *_7* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue