daq2/common: Altera updates
AndreiGrozav
parent
cfd3ea61f1
commit
cac4057449
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@ -40,9 +40,6 @@ add_connection avl_ad9144_xcvr.tx_ip_d_0 avl_ad9144_xcvr.tx_phy_d_0
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add_connection avl_ad9144_xcvr.tx_ip_d_3 avl_ad9144_xcvr.tx_phy_d_1
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add_connection avl_ad9144_xcvr.tx_ip_d_3 avl_ad9144_xcvr.tx_phy_d_1
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add_connection avl_ad9144_xcvr.tx_ip_d_1 avl_ad9144_xcvr.tx_phy_d_2
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add_connection avl_ad9144_xcvr.tx_ip_d_1 avl_ad9144_xcvr.tx_phy_d_2
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add_connection avl_ad9144_xcvr.tx_ip_d_2 avl_ad9144_xcvr.tx_phy_d_3
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add_connection avl_ad9144_xcvr.tx_ip_d_2 avl_ad9144_xcvr.tx_phy_d_3
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add_connection sys_cpu.data_master avl_ad9144_xcvr.core_pll_reconfig
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add_connection sys_cpu.data_master avl_ad9144_xcvr.lane_pll_reconfig
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add_connection sys_cpu.data_master avl_ad9144_xcvr.ip_reconfig
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# ad9144-xcvr
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# ad9144-xcvr
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@ -56,7 +53,6 @@ add_connection sys_clk.clk_reset axi_ad9144_xcvr.s_axi_reset
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add_connection axi_ad9144_xcvr.if_up_rst avl_ad9144_xcvr.rst
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add_connection axi_ad9144_xcvr.if_up_rst avl_ad9144_xcvr.rst
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add_connection avl_ad9144_xcvr.ready axi_ad9144_xcvr.ready
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add_connection avl_ad9144_xcvr.ready axi_ad9144_xcvr.ready
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add_connection axi_ad9144_xcvr.core_pll_locked avl_ad9144_xcvr.core_pll_locked
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add_connection axi_ad9144_xcvr.core_pll_locked avl_ad9144_xcvr.core_pll_locked
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add_connection sys_cpu.data_master axi_ad9144_xcvr.s_axi
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# ad9144-core
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# ad9144-core
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@ -67,7 +63,6 @@ add_connection avl_ad9144_xcvr.core_clk axi_ad9144_core.if_tx_clk
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add_connection axi_ad9144_core.if_tx_data avl_ad9144_xcvr.ip_data
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add_connection axi_ad9144_core.if_tx_data avl_ad9144_xcvr.ip_data
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add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
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add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
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add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
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add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9144_core.s_axi
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# ad9144-unpack
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# ad9144-unpack
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@ -94,11 +89,8 @@ add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout
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add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
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add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
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add_connection sys_clk.clk_reset axi_ad9144_dma.s_axi_reset
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add_connection sys_clk.clk_reset axi_ad9144_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9144_dma.s_axi_clock
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add_connection sys_clk.clk axi_ad9144_dma.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9144_dma.s_axi
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9144_dma.m_src_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9144_dma.m_src_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock
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add_connection axi_ad9144_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
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add_connection sys_cpu.irq axi_ad9144_dma.interrupt_sender
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# ad9680-xcvr
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# ad9680-xcvr
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@ -133,8 +125,6 @@ add_interface rx_sysref conduit end
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set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
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set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
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add_interface rx_sync conduit end
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add_interface rx_sync conduit end
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set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
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set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
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add_connection sys_cpu.data_master avl_ad9680_xcvr.core_pll_reconfig
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add_connection sys_cpu.data_master avl_ad9680_xcvr.ip_reconfig
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# ad9680-xcvr
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# ad9680-xcvr
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@ -148,7 +138,6 @@ add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset
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add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
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add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
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add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
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add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
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add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
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add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
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add_connection sys_cpu.data_master axi_ad9680_xcvr.s_axi
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# ad9680
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# ad9680
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@ -159,7 +148,6 @@ add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof
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add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
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add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
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add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
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add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
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add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9680_core.s_axi
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# ad9680-pack
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# ad9680-pack
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@ -207,71 +195,63 @@ add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
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add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
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add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
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add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
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add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
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add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9680_dma.s_axi
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
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add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
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add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
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# reconfig sharing
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# reconfig sharing
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add_instance avl_adxcfg_0 avl_adxcfg 1.0
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add_instance avl_adxcfg_0 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
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add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
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add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s1
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add_connection avl_adxcfg_0.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_0
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add_connection avl_adxcfg_0.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_0
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add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
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add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
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add_instance avl_adxcfg_1 avl_adxcfg 1.0
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add_instance avl_adxcfg_1 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
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add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
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add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s1
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add_connection avl_adxcfg_1.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_1
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add_connection avl_adxcfg_1.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_1
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add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
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add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
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add_instance avl_adxcfg_2 avl_adxcfg 1.0
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add_instance avl_adxcfg_2 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
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add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
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add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s1
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add_connection avl_adxcfg_2.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_2
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add_connection avl_adxcfg_2.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_2
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add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
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add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
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add_instance avl_adxcfg_3 avl_adxcfg 1.0
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add_instance avl_adxcfg_3 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
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add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
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add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s1
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add_connection avl_adxcfg_3.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_3
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add_connection avl_adxcfg_3.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_3
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add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
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add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
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# addresses
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# addresses
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set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.core_pll_reconfig baseAddress {0x10400000}
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ad_cpu_interconnect 0x10404000 avl_adxcfg_0.rcfg_s0
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set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.ip_reconfig baseAddress {0x10401000}
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ad_cpu_interconnect 0x10504000 avl_adxcfg_0.rcfg_s1
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set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.lane_pll_reconfig baseAddress {0x10402000}
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ad_cpu_interconnect 0x10405000 avl_adxcfg_1.rcfg_s0
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set_connection_parameter_value sys_cpu.data_master/axi_ad9144_dma.s_axi baseAddress {0x1040c000}
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ad_cpu_interconnect 0x10505000 avl_adxcfg_1.rcfg_s1
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set_connection_parameter_value sys_cpu.data_master/axi_ad9144_xcvr.s_axi baseAddress {0x10410000}
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ad_cpu_interconnect 0x10406000 avl_adxcfg_2.rcfg_s0
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set_connection_parameter_value sys_cpu.data_master/axi_ad9144_core.s_axi baseAddress {0x10420000}
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ad_cpu_interconnect 0x10506000 avl_adxcfg_2.rcfg_s1
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set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.core_pll_reconfig baseAddress {0x10500000}
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ad_cpu_interconnect 0x10407000 avl_adxcfg_3.rcfg_s0
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set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.ip_reconfig baseAddress {0x10501000}
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ad_cpu_interconnect 0x10507000 avl_adxcfg_3.rcfg_s1
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set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi baseAddress {0x1050c000}
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ad_cpu_interconnect 0x10400000 avl_ad9144_xcvr.core_pll_reconfig
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set_connection_parameter_value sys_cpu.data_master/axi_ad9680_xcvr.s_axi baseAddress {0x10510000}
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ad_cpu_interconnect 0x10402000 avl_ad9144_xcvr.lane_pll_reconfig
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set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi baseAddress {0x10520000}
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ad_cpu_interconnect 0x10401000 avl_ad9144_xcvr.ip_reconfig
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set_connection_parameter_value axi_ad9144_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
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ad_cpu_interconnect 0x1040c000 axi_ad9144_dma.s_axi
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set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
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ad_cpu_interconnect 0x10410000 axi_ad9144_xcvr.s_axi
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s0 baseAddress {0x10404000}
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ad_cpu_interconnect 0x10420000 axi_ad9144_core.s_axi
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s0 baseAddress {0x10405000}
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ad_cpu_interconnect 0x10500000 avl_ad9680_xcvr.core_pll_reconfig
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s0 baseAddress {0x10406000}
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ad_cpu_interconnect 0x10501000 avl_ad9680_xcvr.ip_reconfig
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s0 baseAddress {0x10407000}
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ad_cpu_interconnect 0x1050c000 axi_ad9680_dma.s_axi
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s1 baseAddress {0x10504000}
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ad_cpu_interconnect 0x10510000 axi_ad9680_xcvr.s_axi
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s1 baseAddress {0x10505000}
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ad_cpu_interconnect 0x10520000 axi_ad9680_core.s_axi
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s1 baseAddress {0x10506000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s1 baseAddress {0x10507000}
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# dma interconnects
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ad_dma_interconnect axi_ad9144_dma.m_src_axi
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ad_dma_interconnect axi_ad9680_dma.m_dest_axi
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# interrupts
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# interrupts
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set_connection_parameter_value sys_cpu.irq/axi_ad9144_dma.interrupt_sender irqNumber {11}
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ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender
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set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
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ad_cpu_interrupt 11 axi_ad9144_dma.interrupt_sender
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