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ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL

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Laszlo Nagy 2021-11-10 16:33:57 +00:00 committed by Laszlo Nagy
parent 731ed0a7a5
commit ca6248ba88
1 changed files with 3 additions and 3 deletions
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projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
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@ -235,9 +235,9 @@ for {set i 0} {$i < $num_quads} {incr i} {
# Clocks and resets
ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk
ad_connect ${ip_name}/gtreset_in ${ip_name}/gt_bridge_ip_0/gtreset_in
ad_connect ${ip_name}/reset_rx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_datapath_in
ad_connect ${ip_name}/reset_tx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_datapath_in
ad_connect GND ${ip_name}/gt_bridge_ip_0/gtreset_in
ad_connect ${ip_name}/reset_rx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_pll_and_datapath_in
ad_connect ${ip_name}/reset_tx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_pll_and_datapath_in
ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \
NUM_PORTS $num_quads \