ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL
parent
731ed0a7a5
commit
ca6248ba88
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@ -235,9 +235,9 @@ for {set i 0} {$i < $num_quads} {incr i} {
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# Clocks and resets
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# Clocks and resets
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ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk
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ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk
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ad_connect ${ip_name}/gtreset_in ${ip_name}/gt_bridge_ip_0/gtreset_in
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ad_connect GND ${ip_name}/gt_bridge_ip_0/gtreset_in
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ad_connect ${ip_name}/reset_rx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_datapath_in
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ad_connect ${ip_name}/reset_rx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_pll_and_datapath_in
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ad_connect ${ip_name}/reset_tx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_datapath_in
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ad_connect ${ip_name}/reset_tx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_pll_and_datapath_in
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ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \
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ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \
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NUM_PORTS $num_quads \
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NUM_PORTS $num_quads \
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