diff --git a/projects/daq2/a10gx/system_stap.qsys b/projects/daq2/a10gx/system_stap.qsys
deleted file mode 100644
index b3d50a1a5..000000000
--- a/projects/daq2/a10gx/system_stap.qsys
+++ /dev/null
@@ -1,86 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-   }
-   element signaltap_ii_logic_analyzer_0
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115S3F45I2SGE2" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="acq_clk"
-   internal="signaltap_ii_logic_analyzer_0.acq_clk"
-   type="clock"
-   dir="end">
-  <port name="acq_clk" internal="acq_clk" />
- </interface>
- <interface
-   name="tap"
-   internal="signaltap_ii_logic_analyzer_0.tap"
-   type="conduit"
-   dir="end">
-  <port name="acq_data_in" internal="acq_data_in" />
-  <port name="acq_trigger_in" internal="acq_trigger_in" />
- </interface>
- <module
-   name="signaltap_ii_logic_analyzer_0"
-   kind="altera_signaltap_ii_logic_analyzer"
-   version="15.0"
-   enabled="1"
-   autoexport="1">
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_num_segments" value="2" />
-  <parameter name="gui_ram_type" value="AUTO" />
-  <parameter name="gui_sq" value="Continuous" />
-  <parameter name="gui_trigger_out_enabled" value="false" />
-  <parameter name="gui_use_segmented" value="false" />
-  <parameter name="sld_data_bits" value="128" />
-  <parameter name="sld_enable_advanced_trigger" value="0" />
-  <parameter name="sld_node_crc_bits" value="32" />
-  <parameter name="sld_node_info" value="806383104" />
-  <parameter name="sld_sample_depth" value="1024" />
-  <parameter name="sld_storage_qualifier_gap_record" value="0" />
-  <parameter name="sld_trigger_bits" value="1" />
-  <parameter name="sld_trigger_in_enabled" value="0" />
-  <parameter name="sld_trigger_level" value="1" />
-  <parameter name="sld_trigger_level_pipeline" value="1" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>