From c9727792175c236bee15516baeead282b71805c3 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 8 Jul 2015 16:23:33 +0300 Subject: [PATCH] motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet - removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core - removed delay related xdc constraints as they are not needed --- .../util_gmii_to_rgmii/util_gmii_to_rgmii.v | 52 +++++++++++++++++++ .../util_gmii_to_rgmii_ip.tcl | 3 ++ .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 6 ++- projects/motcon2_fmc/zed/system_constr.xdc | 18 ------- projects/motcon2_fmc/zed/system_top.v | 42 --------------- 5 files changed, 59 insertions(+), 62 deletions(-) diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v index e0baa9afc..80f72703b 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -43,6 +43,7 @@ module util_gmii_to_rgmii ( clk_20m, clk_25m, clk_125m, + idelayctrl_clk, reset, @@ -69,10 +70,14 @@ module util_gmii_to_rgmii ( gmii_rx_clk); parameter PHY_AD = 5'b10000; + parameter IODELAY_CTRL = 1'b0; + parameter IDELAY_VALUE = 18; + parameter IODELAY_GROUP = "if_delay_group"; input clk_20m; input clk_25m; input clk_125m; + input idelayctrl_clk; input reset; @@ -129,6 +134,9 @@ module util_gmii_to_rgmii ( reg gmii_rx_dv; reg gmii_rx_er; + reg idelayctrl_reset; + reg [ 3:0] idelay_reset_cnt; + assign gigabit = speed_selection [1]; assign gmii_tx_clk = gmii_tx_clk_s; @@ -236,11 +244,13 @@ module util_gmii_to_rgmii ( .I(rgmii_rxc), .O(gmii_rx_clk)); + (* IODELAY_GROUP = IODELAY_GROUP *) IDELAYE2 #( .IDELAY_TYPE("FIXED"), .HIGH_PERFORMANCE_MODE("TRUE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA"), + .IDELAY_VALUE (IDELAY_VALUE), .DELAY_SRC("IDATAIN") ) delay_rgmii_rx_ctl ( .IDATAIN(rgmii_rx_ctl), @@ -258,11 +268,13 @@ module util_gmii_to_rgmii ( generate for (i = 0; i < 4; i = i + 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) IDELAYE2 #( .IDELAY_TYPE("FIXED"), .HIGH_PERFORMANCE_MODE("TRUE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA"), + .IDELAY_VALUE (IDELAY_VALUE), .DELAY_SRC("IDATAIN") ) delay_rgmii_rd ( .IDATAIN(rgmii_rd[i]), @@ -311,4 +323,44 @@ module util_gmii_to_rgmii ( .speed_select(speed_selection), .duplex_mode(duplex_mode)); + // DELAY CONTROLLER + generate + if (IODELAY_CTRL == 1'b1) begin + always @(posedge idelayctrl_clk) begin + if (reset == 1'b1) begin + idelay_reset_cnt <= 4'h0; + idelayctrl_reset <= 1'b1; + end else begin + idelayctrl_reset <= 1'b1; + case (idelay_reset_cnt) + 4'h0: idelay_reset_cnt <= 4'h1; + 4'h1: idelay_reset_cnt <= 4'h2; + 4'h2: idelay_reset_cnt <= 4'h3; + 4'h3: idelay_reset_cnt <= 4'h4; + 4'h4: idelay_reset_cnt <= 4'h5; + 4'h5: idelay_reset_cnt <= 4'h6; + 4'h6: idelay_reset_cnt <= 4'h7; + 4'h7: idelay_reset_cnt <= 4'h8; + 4'h8: idelay_reset_cnt <= 4'h9; + 4'h9: idelay_reset_cnt <= 4'ha; + 4'ha: idelay_reset_cnt <= 4'hb; + 4'hb: idelay_reset_cnt <= 4'hc; + 4'hc: idelay_reset_cnt <= 4'hd; + 4'hd: idelay_reset_cnt <= 4'he; + default: begin + idelay_reset_cnt <= 4'he; + idelayctrl_reset <= 1'b0; + end + endcase + end + end + + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL dlyctrl ( + .RDY(), + .REFCLK(idelayctrl_clk), + .RST(idelayctrl_reset)); + end + endgenerate + endmodule diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl index 2235a95f9..1546e6717 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl @@ -19,4 +19,7 @@ set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]] ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces signal_reset -of_objects [ipx::current_core]]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ + [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] + ipx::save_core [ipx::current_core] diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 304e57245..35e385d3a 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -173,10 +173,11 @@ #ethernet gmii to rgmii converters # phy 1 set gmii_to_rgmii_eth1 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth1 ] - set_property -dict [list CONFIG.PHY_AD {"00000"}] [get_bd_cells gmii_to_rgmii_eth1] + set_property -dict [list CONFIG.PHY_AD {"00000"}] $gmii_to_rgmii_eth1 + set_property -dict [list CONFIG.IODELAY_CTRL {1}] $gmii_to_rgmii_eth1 # phy 2 set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth2 ] - set_property -dict [list CONFIG.PHY_AD {"00001"}] [get_bd_cells gmii_to_rgmii_eth2] + set_property -dict [list CONFIG.PHY_AD {"00001"}] $gmii_to_rgmii_eth2 # iic set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] @@ -378,6 +379,7 @@ ad_connect sys_ps7/ENET0_MDIO_T eth_mdio_t ad_connect sys_ps7/ENET0_MDIO_I eth_mdio_i # phy 1 + ad_connect sys_200m_clk gmii_to_rgmii_eth1/idelayctrl_clk ad_connect gmii_to_rgmii_eth1/gmii sys_ps7/GMII_ETHERNET_0 ad_connect eth1_rgmii gmii_to_rgmii_eth1/rgmii ad_connect gmii_to_rgmii_eth1/reset sys_rstgen/peripheral_reset diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index 8edc4f797..b58a3af61 100755 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -141,21 +141,3 @@ set_clock_groups -asynchronous \ set_clock_groups -asynchronous \ -group [get_clocks {pwm_ctrl_1 }] \ -group [get_clocks {pwm_ctrl_2 }] - -# Ethernet common - -set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] - -# Ethernet 1 -#IDELAY -set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] -set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] -set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] - -# Ethernet 2 -#IDELAY -set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] -set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] -set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] diff --git a/projects/motcon2_fmc/zed/system_top.v b/projects/motcon2_fmc/zed/system_top.v index 5b07ae55e..eaf46fb0c 100644 --- a/projects/motcon2_fmc/zed/system_top.v +++ b/projects/motcon2_fmc/zed/system_top.v @@ -271,16 +271,10 @@ module system_top ( wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; - wire refclk; - wire refclk_rst; - wire eth_mdio_o; wire eth_mdio_i; wire eth_mdio_t; - reg idelayctrl_reset; - reg [ 3:0] idelay_reset_cnt; - // assignments assign fmc_sample_n = gpio_o[32]; @@ -323,40 +317,6 @@ module system_top ( .dio_o(eth_mdio_i), .dio_p(eth_mdio_p)); - always @(posedge refclk) begin - if (refclk_rst == 1'b1) begin - idelay_reset_cnt <= 4'h0; - idelayctrl_reset <= 1'b1; - end else begin - idelayctrl_reset <= 1'b1; - case (idelay_reset_cnt) - 4'h0: idelay_reset_cnt <= 4'h1; - 4'h1: idelay_reset_cnt <= 4'h2; - 4'h2: idelay_reset_cnt <= 4'h3; - 4'h3: idelay_reset_cnt <= 4'h4; - 4'h4: idelay_reset_cnt <= 4'h5; - 4'h5: idelay_reset_cnt <= 4'h6; - 4'h6: idelay_reset_cnt <= 4'h7; - 4'h7: idelay_reset_cnt <= 4'h8; - 4'h8: idelay_reset_cnt <= 4'h9; - 4'h9: idelay_reset_cnt <= 4'ha; - 4'ha: idelay_reset_cnt <= 4'hb; - 4'hb: idelay_reset_cnt <= 4'hc; - 4'hc: idelay_reset_cnt <= 4'hd; - 4'hd: idelay_reset_cnt <= 4'he; - default: begin - idelay_reset_cnt <= 4'he; - idelayctrl_reset <= 1'b0; - end - endcase - end - end - - IDELAYCTRL dlyctrl ( - .RDY(), - .REFCLK(refclk), - .RST(idelayctrl_reset)); - system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -475,8 +435,6 @@ module system_top ( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), - .refclk(refclk), - .refclk_rst(refclk_rst), .otg_vbusoc (otg_vbusoc), .spdif (spdif));