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ad9625_fmc: merge zc706 and vc707

main
Rejeesh Kutty 2014-10-28 10:11:58 -04:00
parent 627da6161b
commit c9691fac64
4 changed files with 11 additions and 55 deletions
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8
projects/ad9625_fmc/common/ad9625_fmc_bd.tcl
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@ -84,6 +84,8 @@ if {$sys_zynq == 1} {
connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9625_fifo/sys_clk] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9625_fifo/sys_clk]
} else { } else {
p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256
} }
# spi # spi
@ -201,6 +203,11 @@ connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data] connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13] connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13]
if {$sys_zynq == 0} {
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_fifo/axi_clk] $sys_200m_clk_source
}
# interconnect (cpu) # interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9625_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9625_dma/s_axi]
@ -327,4 +334,5 @@ if {$sys_zynq == 1} {
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range 0x00200000 -offset 0xc0000000 [get_bd_addr_spaces axi_ad9625_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9625_fifo/axi_bram_ctl/S_AXI/Mem0] SEG_axi_bram_ctl_mem
} }

46
projects/ad9625_fmc/vc707/system_bd.tcl
View File

@ -3,50 +3,4 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
source ../common/ad9625_fmc_bd.tcl source ../common/ad9625_fmc_bd.tcl
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
p_sys_dmafifo [current_bd_instance .] sys_dmafifo 256
delete_bd_objs [get_bd_nets axi_ad9625_adc_clk]
delete_bd_objs [get_bd_nets axi_ad9625_adc_enable]
delete_bd_objs [get_bd_nets axi_ad9625_adc_data]
delete_bd_objs [get_bd_nets axi_ad9625_adc_dovf]
delete_bd_objs [get_bd_nets axi_ad9625_adc_valid]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_dmafifo/axi_clk] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins sys_dmafifo/dma_clk] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_dma/fifo_wr_clk] $sys_200m_clk_source
connect_bd_net -net [get_bd_nets axi_ad9625_gt_rx_rst] [get_bd_pins sys_dmafifo/adc_rst] [get_bd_pins axi_ad9625_gt/rx_rst]
connect_bd_net -net [get_bd_nets sys_200m_resetn] [get_bd_pins sys_dmafifo/dma_rstn] $sys_200m_resetn_source
connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_dma/fifo_wr_xfer_req] [get_bd_pins sys_dmafifo/axi_xfer_req]
connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins sys_dmafifo/adc_clk]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins sys_dmafifo/adc_wr]
connect_bd_net -net axi_ad9625_adc_data [get_bd_pins axi_ad9625_core/adc_data] [get_bd_pins sys_dmafifo/adc_wdata]
connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins sys_dmafifo/adc_wovf]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins sys_dmafifo/dma_wr] [get_bd_pins axi_ad9625_dma/fifo_wr_en]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins sys_dmafifo/dma_wdata] [get_bd_pins axi_ad9625_dma/fifo_wr_din]
connect_bd_net -net axi_ad9625_dma_dovf [get_bd_pins sys_dmafifo/dma_wovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9625_adc_valid [get_bd_pins axi_ad9625_core/adc_valid] [get_bd_pins axi_ad9625_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9625_adc_data [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon
connect_bd_net -net sys_200m_clk [get_bd_pins ila_dma_mon/clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins ila_dma_mon/probe0]
connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins ila_dma_mon/probe1]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins ila_dma_mon/probe2]
connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins sys_dmafifo/axi_xfer_status]
create_bd_addr_seg -range 0x00200000 -offset 0xc0000000 [get_bd_addr_spaces sys_dmafifo/axi_fifo2s/axi] [get_bd_addr_segs sys_dmafifo/axi_bram_ctl/S_AXI/Mem0] SEG_axi_bram_ctl_mem

9
projects/ad9625_fmc/vc707/system_constr.xdc
View File

@ -39,12 +39,3 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd]
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_nets i_system_wrapper/system_i/axi_ad9625_gt_rx_clk] create_clock -name rx_div_clk -period 6.40 [get_nets i_system_wrapper/system_i/axi_ad9625_gt_rx_clk]
set_clock_groups -asynchronous -group {rx_div_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

3
projects/ad9625_fmc/vc707/system_project.tcl
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@ -12,6 +12,9 @@ adi_project_files ad9625_fmc_vc707 [list \
"system_constr.xdc"\ "system_constr.xdc"\
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run ad9625_fmc_vc707 adi_project_run ad9625_fmc_vc707