data_offload: Delete fifo_dst_rlast
parent
4026f2d414
commit
c82b0fb420
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@ -122,7 +122,6 @@ module data_offload #(
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output fifo_dst_resetn,
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output [DST_ADDR_WIDTH-1:0] fifo_dst_raddr,
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input [DST_DATA_WIDTH-1:0] fifo_dst_rdata,
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output fifo_dst_rlast,
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// Status and monitor
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@ -179,7 +178,6 @@ module data_offload #(
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wire m_axis_valid_s;
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wire m_axis_last_s;
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wire [DST_DATA_WIDTH-1:0] m_axis_data_s;
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wire dst_mem_last_s;
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wire dst_mem_valid_s;
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wire dst_mem_valid_int_s;
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wire m_axis_reset_int_s;
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@ -208,7 +206,6 @@ module data_offload #(
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end
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endgenerate
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assign fifo_src_wlast = src_wr_last_s;
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assign fifo_dst_rlast = dst_mem_last_s;
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// Offload FSM and control
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data_offload_fsm #(
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@ -233,7 +230,7 @@ module data_offload #(
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.rd_ready (fifo_dst_ready_int_s),
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.rd_valid (dst_mem_valid_s),
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.rd_addr (fifo_dst_raddr),
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.rd_last (dst_mem_last_s),
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.rd_last (),
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.rd_tkeep (m_axis_tkeep),
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.rd_oneshot (oneshot_s),
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.init_req (init_req),
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@ -273,7 +270,7 @@ module data_offload #(
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.rst (m_axis_reset_int_s),
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.valid (dst_mem_valid_int_s),
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.data (fifo_dst_rdata),
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.last (dst_mem_last_s),
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.last (1'b0),
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.inf_valid (m_axis_valid_s),
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.inf_last (m_axis_last_s),
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.inf_data (m_axis_data_s),
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@ -238,7 +238,7 @@ module data_offload_fsm #(
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if (wr_resetn_in == 1'b0) begin
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wr_last_addr <= {WR_ADDRESS_WIDTH{1'b1}};
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end else begin
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wr_last_addr <= (wr_last && wr_valid_out) ? wr_addr : wr_last_addr;
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wr_last_addr <= (wr_valid_out) ? wr_addr : wr_last_addr;
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end
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end
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@ -105,7 +105,6 @@ proc ad_data_offload_create {instance_name datapath_type mem_type mem_size sourc
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ad_connect fifo2axi_bridge/fifo_dst_ren i_data_offload/fifo_dst_ren
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ad_connect fifo2axi_bridge/fifo_dst_raddr i_data_offload/fifo_dst_raddr
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ad_connect fifo2axi_bridge/fifo_dst_rdata i_data_offload/fifo_dst_rdata
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ad_connect fifo2axi_bridge/fifo_dst_rlast i_data_offload/fifo_dst_rlast
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ad_connect fifo2axi_bridge/fifo_dst_ready i_data_offload/fifo_dst_ready
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}
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