jesd204/tb: support for ModelSim and Xsim

Adding support for ModelSim and Vivado Xsim.

Usage:
  export SIMULATOR=modelsim
    or
  export SIMULATOR=xsim

library/jesd204/axi_jesd204_common/jesd204_up_common.v

@@ -93,6 +93,13 @@ localparam MAX_BEATS_PER_MULTIFRAME = (MAX_OCTETS_PER_FRAME * 32) / DATA_PATH_WI
 
 reg [31:0] up_scratch = 32'h00000000;
 
+reg [7:0] up_cfg_octets_per_frame = 'h00;
+reg [9-DATA_PATH_WIDTH:0] up_cfg_beats_per_multiframe = 'h00;
+reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
+reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
+reg up_cfg_disable_char_replacement = 1'b0;
+reg up_cfg_disable_scrambler = 1'b0;
+
 /* Reset for the register map */
 reg [2:0] up_reset_vector = 3'b111;
 assign up_reset = up_reset_vector[0];
@@ -194,12 +201,6 @@ always @(posedge up_clk) begin
   end
 end
 
-reg [7:0] up_cfg_octets_per_frame = 'h00;
-reg [9-DATA_PATH_WIDTH:0] up_cfg_beats_per_multiframe = 'h00;
-reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
-reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
-reg up_cfg_disable_char_replacement = 1'b0;
-reg up_cfg_disable_scrambler = 1'b0;
 
 wire [20:0] clk_mon_count;
 

library/jesd204/tb/axi_jesd204_rx_regmap_tb.v

@@ -44,7 +44,7 @@
 
 `timescale 1ns/100ps
 
-module axi_jesd204_rx_tb;
+module axi_jesd204_rx_regmap_tb;
   parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd";
   parameter NUM_LANES = 2;
   parameter NUM_LINKS = 1;
@@ -74,6 +74,8 @@ module axi_jesd204_rx_tb;
 
   wire [NUM_LANES*32-1:0] core_status_err_statistics_cnt;
 
+  reg [31:0] expected_reg_mem[0:1023];
+
   task write_reg;
   input [31:0] addr;
   input [31:0] value;
@@ -134,6 +136,9 @@ module axi_jesd204_rx_tb;
     read_reg(addr, value);
     expected = expected_reg_mem[addr[13:2]];
     match <= value === expected;
+    if (value !== expected) begin
+      $display("Address %h, Expected %h, Found %h", addr, expected, value);
+    end
   end
   endtask
 
@@ -145,7 +150,6 @@ module axi_jesd204_rx_tb;
     end
   end
 
-  reg [31:0] expected_reg_mem[0:1023];
 
   task set_reset_reg_value;
   input [31:0] addr;
@@ -257,7 +261,7 @@ module axi_jesd204_rx_tb;
 
     /* Update the expected values */
     for (i = 0; i < NUM_LANES * 'h20; i = i + 'h20) begin
-      lane = i / 20;;
+      lane = i / 20;
       set_reset_reg_value('h300 + i, 'h20);
       set_reset_reg_value('h310 + i, 'h03020100 | {4{lane,4'h0}});
       set_reset_reg_value('h314 + i, 'h07060504 | {4{lane,4'h0}});
@@ -269,6 +273,7 @@ module axi_jesd204_rx_tb;
 
   integer i;
   initial begin
+    #1;
     initialize_expected_reg_mem();
     @(posedge s_axi_aresetn)
     check_all_registers();

library/jesd204/tb/axi_jesd204_tx_regmap_tb.v

@@ -44,7 +44,7 @@
 
 `timescale 1ns/100ps
 
-module axi_jesd204_tx_tb;
+module axi_jesd204_tx_regmap_tb;
   parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd";
   parameter NUM_LANES = 2;
   parameter NUM_LINKS = 2;
@@ -72,6 +72,8 @@ module axi_jesd204_tx_tb;
   wire [1:0] s_axi_rresp;
   wire [31:0] s_axi_rdata;
 
+  reg [31:0] expected_reg_mem[0:1023];
+
   task write_reg;
   input [31:0] addr;
   input [31:0] value;
@@ -143,7 +145,6 @@ module axi_jesd204_tx_tb;
     end
   end
 
-  reg [31:0] expected_reg_mem[0:1023];
 
   task set_reset_reg_value;
   input [31:0] addr;

library/jesd204/tb/loopback_tb.v

@@ -68,6 +68,7 @@ module loopback_tb;
   wire rx_valid;
   wire [NUM_LANES*32-1:0] rx_data;
   reg data_mismatch = 1'b1;
+  wire [NUM_LINKS-1:0] sync;
 
   always @(posedge clk) begin
     if (sync == 1'b0) begin
@@ -98,7 +99,6 @@ module loopback_tb;
   wire [NUM_LANES*4-1:0] phy_charisk_out;
   wire [NUM_LANES*32-1:0] phy_data_in;
   wire [NUM_LANES*4-1:0] phy_charisk_in;
-  wire [NUM_LINKS-1:0] sync;
 
   reg [5:0] sysref_counter = 'h00;
   reg sysref_rx = 1'b0;

library/jesd204/tb/run_tb.sh

@@ -1,8 +1,24 @@
 NAME=`basename $0`
 
-mkdir -p run
-mkdir -p vcd
-iverilog ${SOURCE} -o run/run_${NAME} $1 || exit 1
-
-cd vcd
-../run/run_${NAME}
+case "$SIMULATOR" in
+	  modelsim)
+  		# ModelSim flow
+  		vlib work
+  		vlog ${SOURCE} || exit 1
+  		vsim ${NAME} -do "add log /* -r; run -a" -gui || exit 1
+		;;
+  	xsim)
+  		# xsim flow
+  		xvlog -log ${NAME}_xvlog.log --sourcelibdir . ${SOURCE}
+  		xelab -log ${NAME}_xelab.log -debug all ${NAME}
+  		xsim work.${NAME} -R
+		;;
+	  *)
+      mkdir -p run
+      mkdir -p vcd
+      iverilog ${SOURCE} -o run/run_${NAME} $1 || exit 1
+  
+      cd vcd
+      ../run/run_${NAME}
+	  ;;
+esac

library/jesd204/tb/soft_pcs_8b10b_table_tb.v

@@ -70,6 +70,9 @@ module soft_pcs_8b10b_table_tb;
   reg build_k28 = 1'b0;
   reg build_table = 1'b1;
 
+  reg decoder_disparity = 1'b0;
+  wire decoder_disparity_s;
+
   always @(posedge clk) begin
     counter <= counter + 1'b1;
 
@@ -119,9 +122,6 @@ module soft_pcs_8b10b_table_tb;
     end
   end
 
-  reg decoder_disparity = 1'b0;
-  wire decoder_disparity_s;
-
   always @(posedge clk) begin
   end
 

library/jesd204/tb/tb_base.v

@@ -43,7 +43,7 @@
 //
 
 
-  reg clk = 1'b1;
+  reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;
   reg trigger_reset = 1'b0;
   wire reset;