From c6b065c349943b397bc1d692da98c6be367c54b4 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 22 Aug 2016 16:48:52 +0300 Subject: [PATCH] zc706: Updated DDR3 dacfifo --- projects/common/zc706/zc706_system_plddr3_dacfifo.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl index 2c2281846..c59030039 100644 --- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl +++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl @@ -35,7 +35,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} { create_bd_pin -dir O ddr_clk - set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] + set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl