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zc706: Updated DDR3 dacfifo

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Adrian Costina 2016-08-22 16:48:52 +03:00
parent f697490de6
commit c6b065c349
1 changed files with 1 additions and 1 deletions
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projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
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@ -35,7 +35,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
create_bd_pin -dir O ddr_clk
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl