From c5b1b905e311db86bc52551627f00c208769da47 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 12 Apr 2018 14:12:00 +0200 Subject: [PATCH] ad_sysref_gen: Fix quartus warnings Fix the following warnings that are generated by Quartus: Warning (10230): Verilog HDL assignment warning at ad_sysref_gen.v(68): truncated value with size 32 to match size of target (8) No functional changes. Signed-off-by: Lars-Peter Clausen --- library/common/ad_sysref_gen.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/common/ad_sysref_gen.v b/library/common/ad_sysref_gen.v index c2c1abe9d..1b255eab2 100644 --- a/library/common/ad_sysref_gen.v +++ b/library/common/ad_sysref_gen.v @@ -65,9 +65,9 @@ module ad_sysref_gen ( // free running counter for periodic SYSREF generation always @(posedge core_clk) begin if (sysref_en_int) begin - counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1 : 0; + counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1'b1 : 8'h0; end else begin - counter <= 0; + counter <= 8'h0; end end