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ad_sysref_gen: Fix quartus warnings 

Fix the following warnings that are generated by Quartus:
	Warning (10230): Verilog HDL assignment warning at ad_sysref_gen.v(68): truncated value with size 32 to match size of target (8)

No functional changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Lars-Peter Clausen 2018-04-12 14:12:00 +02:00 committed by Lars-Peter Clausen
parent 162248375c
commit c5b1b905e3
1 changed files with 2 additions and 2 deletions
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4
library/common/ad_sysref_gen.v
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@ -65,9 +65,9 @@ module ad_sysref_gen (
// free running counter for periodic SYSREF generation
always @(posedge core_clk) begin
if (sysref_en_int) begin
counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1 : 0;
counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1'b1 : 8'h0;
end else begin
counter <= 0;
counter <= 8'h0;
end
end