diff --git a/library/Makefile b/library/Makefile index 08a7551c1..7b7b4e429 100644 --- a/library/Makefile +++ b/library/Makefile @@ -39,6 +39,8 @@ clean: make -C axi_mc_current_monitor clean make -C axi_mc_speed clean make -C axi_spdif_tx clean + make -C cn0363/cn0363_dma_sequencer clean + make -C cn0363/cn0363_phase_data_sync clean make -C controllerperipheralhdladi_pcore clean make -C cordic_demod clean make -C spi_engine/axi_spi_engine clean @@ -97,6 +99,8 @@ lib: -make -C axi_mc_current_monitor -make -C axi_mc_speed -make -C axi_spdif_tx + -make -C cn0363/cn0363_dma_sequencer + -make -C cn0363/cn0363_phase_data_sync -make -C controllerperipheralhdladi_pcore -make -C cordic_demod -make -C spi_engine/axi_spi_engine diff --git a/library/cn0363/cn0363_dma_sequencer/Makefile b/library/cn0363/cn0363_dma_sequencer/Makefile new file mode 100644 index 000000000..29972c388 --- /dev/null +++ b/library/cn0363/cn0363_dma_sequencer/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS := cn0363_dma_sequencer_ip.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += cn0363_dma_sequencer.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: cn0363_dma_sequencer.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +cn0363_dma_sequencer.xpr: $(M_DEPS) + rm -rf $(M_FLIST) + $(M_VIVADO) cn0363_dma_sequencer_ip.tcl >> cn0363_dma_sequencer_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v new file mode 100644 index 000000000..dac6814b8 --- /dev/null +++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v @@ -0,0 +1,160 @@ +module cn0363_dma_sequencer ( + input clk, + input resetn, + + input [31:0] phase, + input phase_valid, + output reg phase_ready, + + input [23:0] data, + input data_valid, + output reg data_ready, + + input [31:0] data_filtered, + input data_filtered_valid, + output reg data_filtered_ready, + + input [31:0] i_q, + input i_q_valid, + output reg i_q_ready, + + input [31:0] i_q_filtered, + input i_q_filtered_valid, + output reg i_q_filtered_ready, + + output overflow, + + output reg [31:0] dma_wr_data, + output reg dma_wr_en, + output reg dma_wr_sync, + input dma_wr_overflow, + input dma_wr_xfer_req, + + input [13:0] channel_enable, + + output processing_resetn +); + +reg [3:0] count = 'h00; + +assign overflow = dma_wr_overflow; +assign processing_resetn = dma_wr_xfer_req; + +always @(posedge clk) begin + if (processing_resetn == 1'b0) begin + count <= 'h0; + end else begin + case (count) + 'h0: if (phase_valid) count <= count + 1; + 'h1: if (data_valid) count <= count + 1; + 'h2: if (data_filtered_valid) count <= count + 1; + 'h3: if (i_q_valid) count <= count + 1; + 'h4: if (i_q_valid) count <= count + 1; + 'h5: if (i_q_filtered_valid) count <= count + 1; + 'h6: if (i_q_filtered_valid) count <= count + 1; + 'h7: if (phase_valid) count <= count + 1; + 'h8: if (data_valid) count <= count + 1; + 'h9: if (data_filtered_valid) count <= count + 1; + 'ha: if (i_q_valid) count <= count + 1; + 'hb: if (i_q_valid) count <= count + 1; + 'hc: if (i_q_filtered_valid) count <= count + 1; + 'hd: if (i_q_filtered_valid) count <= 'h00; + endcase + end +end + +always @(posedge clk) begin + case (count) + 'h0: dma_wr_data <= phase; + 'h1: dma_wr_data <= {8'h00,data[23:0]}; + 'h2: dma_wr_data <= data_filtered; + 'h3: dma_wr_data <= i_q; + 'h4: dma_wr_data <= i_q; + 'h5: dma_wr_data <= i_q_filtered; + 'h6: dma_wr_data <= i_q_filtered; + 'h7: dma_wr_data <= phase; + 'h8: dma_wr_data <= {8'h00,data[23:0]}; + 'h9: dma_wr_data <= data_filtered; + 'ha: dma_wr_data <= i_q; + 'hb: dma_wr_data <= i_q; + 'hc: dma_wr_data <= i_q_filtered; + 'hd: dma_wr_data <= i_q_filtered; + endcase +end + +always @(posedge clk) begin + if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin + dma_wr_en <= 1'b0; + end else begin + case (count) + 'h0: dma_wr_en <= phase_valid; + 'h1: dma_wr_en <= data_valid; + 'h2: dma_wr_en <= data_filtered_valid; + 'h3: dma_wr_en <= i_q_valid; + 'h4: dma_wr_en <= i_q_valid; + 'h5: dma_wr_en <= i_q_filtered_valid; + 'h6: dma_wr_en <= i_q_filtered_valid; + 'h7: dma_wr_en <= phase_valid; + 'h8: dma_wr_en <= data_valid; + 'h9: dma_wr_en <= data_filtered_valid; + 'ha: dma_wr_en <= i_q_valid; + 'hb: dma_wr_en <= i_q_valid; + 'hc: dma_wr_en <= i_q_filtered_valid; + 'hd: dma_wr_en <= i_q_filtered_valid; + endcase + end +end + +always @(posedge clk) begin + if (count == 'h00) begin + dma_wr_sync <= 1'b1; + end else if (dma_wr_en == 1'b1) begin + dma_wr_sync = 1'b0; + end +end + +always @(*) begin + case (count) + 'h0: phase_ready <= 1'b1; + 'h7: phase_ready <= 1'b1; + default: phase_ready <= 1'b0; + endcase +end + +always @(*) begin + case (count) + 'h1: data_ready <= 1'b1; + 'h8: data_ready <= 1'b1; + default: data_ready <= 1'b0; + endcase +end + +always @(*) begin + case (count) + 'h2: data_filtered_ready <= 1'b1; + 'h9: data_filtered_ready <= 1'b1; + default: data_filtered_ready <= 1'b0; + endcase +end + +always @(*) begin + case (count) + 'h3: i_q_ready <= 1'b1; + 'h4: i_q_ready <= 1'b1; + 'ha: i_q_ready <= 1'b1; + 'hb: i_q_ready <= 1'b1; + default: i_q_ready <= 1'b0; + endcase +end + +always @(*) begin + case (count) + 'h5: i_q_filtered_ready <= 1'b1; + 'h6: i_q_filtered_ready <= 1'b1; + 'hc: i_q_filtered_ready <= 1'b1; + 'hd: i_q_filtered_ready <= 1'b1; + default: i_q_filtered_ready <= 1'b0; + endcase +end + +endmodule diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl new file mode 100644 index 000000000..77d41a487 --- /dev/null +++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl @@ -0,0 +1,72 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create cn0363_dma_sequencer +adi_ip_files cn0363_dma_sequencer [list \ + "cn0363_dma_sequencer.v" +] + +adi_ip_properties_lite cn0363_dma_sequencer + +adi_add_bus "phase" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"phase_valid" "TVALID"} \ + {"phase_ready" "TREADY"} \ + {"phase" "TDATA"} \ + } + +adi_add_bus "data" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"data_valid" "TVALID"} \ + {"data_ready" "TREADY"} \ + {"data" "TDATA"} \ + } + +adi_add_bus "data_filtered" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"data_filtered_valid" "TVALID"} \ + {"data_filtered_ready" "TREADY"} \ + {"data_filtered" "TDATA"} \ + } + +adi_add_bus "i_q" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"i_q_valid" "TVALID"} \ + {"i_q_ready" "TREADY"} \ + {"i_q" "TDATA"} \ + } + +adi_add_bus "i_q_filtered" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"i_q_filtered_valid" "TVALID"} \ + {"i_q_filtered_ready" "TREADY"} \ + {"i_q_filtered" "TDATA"} \ + } + + +adi_add_bus "dma_wr" "master" \ + "analog.com:interface:fifo_wr_rtl:1.0" \ + "analog.com:interface:fifo_wr:1.0" \ + { + {"dma_wr_en" "EN"} \ + {"dma_wr_sync" "SYNC"} \ + {"dma_wr_data" "DATA"} \ + {"dma_wr_overflow" "OVERFLOW"} \ + {"dma_wr_xfer_req" "XFER_REQ"} \ + } + + +adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "resetn:processing_resetn" + +ipx::save_core [ipx::current_core] diff --git a/library/cn0363/cn0363_phase_data_sync/Makefile b/library/cn0363/cn0363_phase_data_sync/Makefile new file mode 100644 index 000000000..33cf98cdd --- /dev/null +++ b/library/cn0363/cn0363_phase_data_sync/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS := cn0363_phase_data_sync_ip.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += cn0363_phase_data_sync.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: cn0363_phase_data_sync.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +cn0363_phase_data_sync.xpr: $(M_DEPS) + rm -rf $(M_FLIST) + $(M_VIVADO) cn0363_phase_data_sync_ip.tcl >> cn0363_phase_data_sync_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v new file mode 100644 index 000000000..c2bb1310b --- /dev/null +++ b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v @@ -0,0 +1,131 @@ + + +module cn0363_phase_data_sync ( + input clk, + input resetn, + + input processing_resetn, + + output s_axis_sample_ready, + input s_axis_sample_valid, + input [7:0] s_axis_sample_data, + + input sample_has_stat, + + input conv_done, + input [31:0] phase, + + output reg m_axis_sample_valid, + input m_axis_sample_ready, + output [23:0] m_axis_sample_data, + + output reg m_axis_phase_valid, + input m_axis_phase_ready, + output [31:0] m_axis_phase_data, + + output reg overflow +); + +reg [1:0] data_counter = 'h00; + +reg [31:0] phase_hold = 'h00; +reg [23:0] sample_hold = 'h00; +reg sample_hold_valid = 1'b0; +reg conv_done_d1 = 1'b0; + +reg synced = 1'b0; +wire sync; + +/* The ADC will do conversions regardless of whether the pipeline is ready or + not. So we'll always accept new samples and assert overflow if necessary if + the pipeline is not ready. */ +assign s_axis_sample_ready = 1'b1; + +// Conversion from offset binary to signed on data +assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]}; +assign m_axis_phase_data = phase_hold; + +always @(posedge clk) begin + if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin + // Is the processing pipeline ready to accept data? + if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin + overflow <= 1'b1; + end else begin + phase_hold <= phase; + overflow <= 1'b0; + end + end else begin + overflow <= 1'b0; + end + conv_done_d1 <= conv_done; +end + +always @(posedge clk) begin + if (processing_resetn == 1'b0) begin + m_axis_phase_valid <= 1'b0; + m_axis_sample_valid <= 1'b0; + end else begin + /* Data and phase become valid once we have both */ + if (sample_hold_valid == 1'b1) begin + m_axis_phase_valid <= 1'b1; + m_axis_sample_valid <= 1'b1; + end else begin + if (m_axis_phase_ready == 1'b1) begin + m_axis_phase_valid <= 1'b0; + end + if (m_axis_sample_ready == 1'b1) begin + m_axis_sample_valid <= 1'b0; + end + end + end +end + +/* If the STAT register is included in the sample we get 4 bytes per sample and + * are able to detect channel swaps and synchronize the first output sample to + * the first channel. If the STAT register is not included we only get 3 bytes + * per sample and rely on that the first sample will always be from the first + * channel */ + +always @(posedge clk) begin + sample_hold_valid <= 1'b0; + if (sample_has_stat == 1'b0) begin + if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin + sample_hold_valid <= 1'b1; + end + end else begin + if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 && + (sync == 1'b1 || synced == 1'b1)) begin + sample_hold_valid <= 1'b1; + end + end +end + +always @(posedge clk) begin + if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin + sample_hold <= {sample_hold[15:0],s_axis_sample_data}; + end +end + +always @(posedge clk) begin + if (s_axis_sample_valid == 1'b1) begin + if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin + data_counter <= 2'h0; + end else begin + data_counter <= data_counter + 1'b1; + end + end +end + +assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3; + +always @(posedge clk) begin + if (processing_resetn == 1'b0) begin + synced <= ~sample_has_stat; + end else begin + if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin + synced <= 1'b1; + end + end +end + +endmodule diff --git a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl new file mode 100644 index 000000000..3dde13021 --- /dev/null +++ b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl @@ -0,0 +1,41 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create cn0363_phase_data_sync +adi_ip_files cn0363_phase_data_sync [list \ + "cn0363_phase_data_sync.v" +] + +adi_ip_properties_lite cn0363_phase_data_sync + +adi_add_bus "S_AXIS_SAMPLE" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_sample_valid" "TVALID"} \ + {"s_axis_sample_ready" "TREADY"} \ + {"s_axis_sample_data" "TDATA"} \ + } + +adi_add_bus "M_AXIS_SAMPLE" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_sample_valid" "TVALID"} \ + {"m_axis_sample_ready" "TREADY"} \ + {"m_axis_sample_data" "TDATA"} \ + } + +adi_add_bus "M_AXIS_PHASE" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_phase_valid" "TVALID"} \ + {"m_axis_phase_ready" "TREADY"} \ + {"m_axis_phase_data" "TDATA"} \ + } + +adi_add_bus_clock "clk" "S_AXIS_SAMPLE:M_AXIS_SAMPLE:M_AXIS_PHASE" "resetn" + +ipx::save_core [ipx::current_core] diff --git a/projects/Makefile b/projects/Makefile index 0ab5d5ff2..655a28251 100644 --- a/projects/Makefile +++ b/projects/Makefile @@ -15,6 +15,7 @@ all: -make -C adv7511 all -make -C cftl_cip all -make -C cftl_std all + -make -C cn0363 all -make -C daq1 all -make -C daq2 all -make -C daq3 all @@ -43,6 +44,7 @@ clean: make -C adv7511 clean make -C cftl_cip clean make -C cftl_std clean + make -C cn0363 clean make -C daq1 clean make -C daq2 clean make -C daq3 clean @@ -71,6 +73,7 @@ clean-all: make -C adv7511 clean-all make -C cftl_cip clean-all make -C cftl_std clean-all + make -C cn0363 clean-all make -C daq1 clean-all make -C daq2 clean-all make -C daq3 clean-all diff --git a/projects/cn0363/zed/filters/hpf.mat b/projects/cn0363/zed/filters/hpf.mat new file mode 100644 index 000000000..f3b6558c8 --- /dev/null +++ b/projects/cn0363/zed/filters/hpf.mat @@ -0,0 +1,520 @@ +# Created by Octave 3.6.2, Tue Apr 07 15:22:27 2015 CEST +# name: hpf +# type: matrix +# rows: 513 +# columns: 1 + 3.125005230091648e-06 + 1.272922340541526e-05 + 2.228713693195711e-05 + 3.167779216011667e-05 + 4.077961244411042e-05 + 4.947137642943441e-05 + 5.763325048199676e-05 + 6.514788075089597e-05 + 7.190154838608252e-05 + 7.778538895546582e-05 + 8.269667417994694e-05 + 8.654015080185192e-05 + 8.922942780916198e-05 + 9.068839945428162e-05 + 9.08526876417122e-05 + 8.967108343167956e-05 + 8.710696373934456e-05 + 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-7.664080993357286e-05 + -7.666439125225632e-05 + + diff --git a/projects/cn0363/zed/system_bd.tcl b/projects/cn0363/zed/system_bd.tcl new file mode 100644 index 000000000..b769b2a63 --- /dev/null +++ b/projects/cn0363/zed/system_bd.tcl @@ -0,0 +1,300 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + +proc load_fir_filter_vector {filter_file} { + set fp [open $filter_file r] + set data [split [read $fp] "\n"] + set filter "" + close $fp + foreach line $data { + set line [string trim $line] + if {[string equal -length 1 $line "#"] || $line eq ""} { + continue + } + if {$filter ne ""} { + append filter "," + } + append filter $line + } + + return $filter +} + +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7 + +set_property LEFT 34 [get_bd_ports GPIO_I] +set_property LEFT 34 [get_bd_ports GPIO_O] +set_property LEFT 34 [get_bd_ports GPIO_T] + +set axi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma] +set_property -dict [list \ + CONFIG.C_FIFO_SIZE 2 \ + CONFIG.C_DMA_TYPE_SRC 2 \ + CONFIG.C_DMA_TYPE_DEST 0 \ + CONFIG.C_CYCLIC 0 \ + CONFIG.C_SYNC_TRANSFER_START 1 \ + CONFIG.C_AXI_SLICE_SRC 0 \ + CONFIG.C_AXI_SLICE_DEST 0 \ + CONFIG.C_CLKS_ASYNC_DEST_REQ 0 \ + CONFIG.C_CLKS_ASYNC_SRC_DEST 0 \ + CONFIG.C_CLKS_ASYNC_REQ_SRC 0 \ + CONFIG.C_2D_TRANSFER 0 \ + CONFIG.C_DMA_DATA_WIDTH_SRC 32 \ + CONFIG.C_DMA_DATA_WIDTH_DEST 64 \ + CONFIG.C_DMA_AXI_PROTOCOL_DEST 1 \ + ] $axi_dma + +# Create SPI engine controller with offload +create_bd_cell -type hier spi +current_bd_instance /spi + + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir O conv_done + create_bd_pin -dir O irq + create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE + + set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution] + set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi] + set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload] + set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect] + set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi] + + set_property -dict [list CONFIG.NUM_CS 2] $spi_engine + + set_property -dict [list CONFIG.NUM_CS 2] $util_sigma_delta_spi + + ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl + ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl + ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl + ad_connect interconnect/m_ctrl execution/ctrl + ad_connect offload/offload_sdi M_AXIS_SAMPLE + + ad_connect util_sigma_delta_spi/data_ready offload/trigger + ad_connect util_sigma_delta_spi/data_ready conv_done + + ad_connect execution/active util_sigma_delta_spi/spi_active + ad_connect execution/spi util_sigma_delta_spi/s_spi + ad_connect util_sigma_delta_spi/m_spi m_spi + + connect_bd_net \ + [get_bd_pins clk] \ + [get_bd_pins offload/spi_clk] \ + [get_bd_pins offload/ctrl_clk] \ + [get_bd_pins execution/clk] \ + [get_bd_pins axi/s_axi_aclk] \ + [get_bd_pins axi/spi_clk] \ + [get_bd_pins interconnect/clk] \ + [get_bd_pins util_sigma_delta_spi/clk] + + connect_bd_net \ + [get_bd_pins axi/spi_resetn] \ + [get_bd_pins offload/spi_resetn] \ + [get_bd_pins execution/resetn] \ + [get_bd_pins interconnect/resetn] \ + [get_bd_pins util_sigma_delta_spi/resetn] + + connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn] + ad_connect irq axi/irq + +current_bd_instance / + +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi +ad_connect spi/m_spi spi + +set phase_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 phase_gen] +set phase_slice [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 phase_slice] +create_bd_port -dir O excitation + +set excitation_freq 1020 + +set_property -dict [list \ + CONFIG.Output_Width 32 \ + CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]] \ + ] $phase_gen + +set_property -dict [list \ + CONFIG.DIN_TO {31} \ + CONFIG.DIN_FROM {31} \ + CONFIG.DOUT_WIDTH {1} \ + ] $phase_slice + +ad_connect /phase_gen/Q /phase_slice/Din +ad_connect /phase_slice/Dout excitation + +create_bd_cell -type hier processing +current_bd_instance /processing + + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir I conv_done + create_bd_pin -dir I -from 31 -to 0 phase + create_bd_pin -dir O overflow + create_bd_pin -dir I -from 13 -to 0 channel_enable + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE + create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR + + create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync + create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer + create_bd_cell -type ip -vlnv analog.com:user:cordic_demod:1.0 cordic_demod + + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 phase_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_filtered_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 i_q_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_combiner:1.1 phase_sample_combine + set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize] + + set_property -dict [list \ + CONFIG.C_M_DATA_WIDTH 32 \ + CONFIG.C_S_DATA_WIDTH 64 \ + ] $i_q_resize + + set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf] + set lpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 lpf] + + set_property -dict [list \ + CONFIG.Data_Fractional_Bits.VALUE_SRC USER \ + CONFIG.Data_Sign.VALUE_SRC USER \ + CONFIG.Data_Width.VALUE_SRC USER \ + CONFIG.M_DATA_Has_TREADY true \ + CONFIG.Number_Channels 2 \ + CONFIG.Sample_Frequency 0.025 \ + CONFIG.Clock_Frequency 100 \ + CONFIG.Coefficient_Width 16 \ + CONFIG.Data_Width 24 \ + CONFIG.Output_Width 32 \ + CONFIG.Output_Rounding_Mode Truncate_LSBs \ + CONFIG.Has_ARESETn true \ + CONFIG.Reset_Data_Vector false \ + CONFIG.CoefficientVector [load_fir_filter_vector "filters/hpf.mat"] \ + ] $hpf + + set_property -dict [list \ + CONFIG.Data_Fractional_Bits.VALUE_SRC USER \ + CONFIG.Data_Sign.VALUE_SRC USER \ + CONFIG.Data_Width.VALUE_SRC USER \ + CONFIG.M_DATA_Has_TREADY true \ + CONFIG.Number_Channels 4 \ + CONFIG.Sample_Frequency 0.025 \ + CONFIG.Clock_Frequency 100 \ + CONFIG.Coefficient_Width 24 \ + CONFIG.Data_Width 32 \ + CONFIG.Output_Width 32 \ + CONFIG.Output_Rounding_Mode Truncate_LSBs \ + CONFIG.Has_ARESETn true \ + CONFIG.Reset_Data_Vector false \ + CONFIG.CoefficientVector [load_fir_filter_vector "filters/lpf.mat"] \ + ] $lpf + + set overflow_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 overflow_or] + set_property -dict [list \ + CONFIG.C_SIZE 1 \ + CONFIG.C_OPERATION {or} \ + ] $overflow_or + + ad_connect S_AXIS_SAMPLE phase_data_sync/S_AXIS_SAMPLE + ad_connect conv_done phase_data_sync/conv_done + ad_connect phase phase_data_sync/phase + + ad_connect phase_data_sync/M_AXIS_PHASE phase_broadcast/S_AXIS + ad_connect phase_broadcast/M00_AXIS sequencer/phase + ad_connect phase_broadcast/M01_AXIS phase_sample_combine/S01_AXIS + + ad_connect phase_data_sync/M_AXIS_SAMPLE sample_broadcast/S_AXIS + ad_connect sample_broadcast/M00_AXIS sequencer/data + ad_connect sample_broadcast/M01_AXIS hpf/S_AXIS_DATA + + ad_connect hpf/M_AXIS_DATA sample_filtered_broadcast/S_AXIS + ad_connect sample_filtered_broadcast/M00_AXIS sequencer/data_filtered + ad_connect sample_filtered_broadcast/M01_AXIS phase_sample_combine/S00_AXIS + + ad_connect phase_sample_combine/M_AXIS cordic_demod/S_AXIS + ad_connect cordic_demod/M_AXIS i_q_resize/s_axis + + ad_connect i_q_resize/m_axis i_q_broadcast/S_AXIS + ad_connect i_q_broadcast/M00_AXIS sequencer/i_q + ad_connect i_q_broadcast/M01_AXIS lpf/S_AXIS_DATA + + ad_connect lpf/M_AXIS_DATA sequencer/i_q_filtered + + connect_bd_net \ + [get_bd_pins clk] \ + [get_bd_pins phase_data_sync/clk] \ + [get_bd_pins sequencer/clk] \ + [get_bd_pins cordic_demod/clk] \ + [get_bd_pins phase_broadcast/aclk] \ + [get_bd_pins sample_broadcast/aclk] \ + [get_bd_pins sample_filtered_broadcast/aclk] \ + [get_bd_pins i_q_broadcast/aclk] \ + [get_bd_pins phase_sample_combine/aclk] \ + [get_bd_pins i_q_resize/clk] \ + [get_bd_pins hpf/aclk] \ + [get_bd_pins lpf/aclk] + + connect_bd_net \ + [get_bd_pins resetn] \ + [get_bd_pins sequencer/resetn] \ + [get_bd_pins phase_data_sync/resetn] \ + + connect_bd_net \ + [get_bd_pins sequencer/processing_resetn] \ + [get_bd_pins phase_data_sync/processing_resetn] \ + [get_bd_pins cordic_demod/resetn] \ + [get_bd_pins phase_broadcast/aresetn] \ + [get_bd_pins sample_broadcast/aresetn] \ + [get_bd_pins sample_filtered_broadcast/aresetn] \ + [get_bd_pins i_q_broadcast/aresetn] \ + [get_bd_pins phase_sample_combine/aresetn] \ + [get_bd_pins i_q_resize/resetn] \ + [get_bd_pins hpf/aresetn] \ + [get_bd_pins lpf/aresetn] + + ad_connect channel_enable sequencer/channel_enable + ad_connect sequencer/dma_wr DMA_WR + + ad_connect phase_data_sync/overflow overflow_or/Op1 + ad_connect sequencer/overflow overflow_or/Op2 + ad_connect overflow_or/Res overflow + + ad_connect phase_data_sync/sample_has_stat GND + +current_bd_instance / + +ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE +ad_connect /spi/conv_done /processing/conv_done +ad_connect /phase_gen/Q /processing/phase + +set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc] +set_property -dict [list \ + CONFIG.NUM_CHANNELS 14 \ + ] $axi_adc + +ad_connect processing/overflow axi_adc/adc_dovf +ad_connect axi_adc/adc_enable processing/channel_enable + +connect_bd_net -net sys_cpu_clk \ + [get_bd_pins /spi/clk] \ + [get_bd_pins /processing/clk] \ + [get_bd_pins /axi_dma/m_dest_axi_aclk] \ + [get_bd_pins /axi_dma/fifo_wr_clk] \ + [get_bd_pins /phase_gen/CLK] \ + [get_bd_pins /axi_adc/adc_clk] + +connect_bd_net -net sys_cpu_resetn \ + [get_bd_pins /spi/resetn] \ + [get_bd_pins /processing/resetn] \ + [get_bd_pins /axi_dma/m_dest_axi_aresetn] + +ad_connect /processing/dma_wr /axi_dma/fifo_wr + +ad_cpu_interconnect 0x43c00000 /axi_adc +ad_cpu_interconnect 0x44a00000 /spi/axi +ad_cpu_interconnect 0x44a30000 /axi_dma + +ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" /spi/irq + +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_dma/m_dest_axi diff --git a/projects/cn0363/zed/system_constr.xdc b/projects/cn0363/zed/system_constr.xdc new file mode 100644 index 000000000..78e372dd0 --- /dev/null +++ b/projects/cn0363/zed/system_constr.xdc @@ -0,0 +1,23 @@ + +# PMOD JA + +set_property PACKAGE_PIN Y11 [get_ports gain0_o] +set_property IOSTANDARD LVCMOS33 [get_ports gain0_o] +set_property PACKAGE_PIN AA11 [get_ports gain1_o] +set_property IOSTANDARD LVCMOS33 [get_ports gain1_o] +set_property PACKAGE_PIN AA9 [get_ports led_clk_o] +set_property IOSTANDARD LVCMOS33 [get_ports led_clk_o] +set_property PACKAGE_PIN Y10 [get_ports {spi_cs[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[1]}] + +set_property PACKAGE_PIN AB11 [get_ports {spi_cs[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[0]}] +set_property PACKAGE_PIN AB10 [get_ports spi_sdo] +set_property IOSTANDARD LVCMOS33 [get_ports spi_sdo] +set_property PULLUP true [get_ports spi_sdo] +set_property PACKAGE_PIN AB9 [get_ports spi_sdi] +set_property IOSTANDARD LVCMOS33 [get_ports spi_sdi] +set_property PULLUP true [get_ports spi_sdi] +set_property PACKAGE_PIN AA8 [get_ports spi_sclk] +set_property IOSTANDARD LVCMOS33 [get_ports spi_sclk] + diff --git a/projects/cn0363/zed/system_project.tcl b/projects/cn0363/zed/system_project.tcl new file mode 100644 index 000000000..9aff54995 --- /dev/null +++ b/projects/cn0363/zed/system_project.tcl @@ -0,0 +1,12 @@ +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create cn0363_zed +adi_project_files cn0363_zed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v"] + +adi_project_run cn0363_zed diff --git a/projects/cn0363/zed/system_top.v b/projects/cn0363/zed/system_top.v new file mode 100644 index 000000000..b2b39d75e --- /dev/null +++ b/projects/cn0363/zed/system_top.v @@ -0,0 +1,276 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + spdif, + + iic_scl, + iic_sda, + iic_mux_scl, + iic_mux_sda, + + spi_sdo, + spi_sdi, + spi_cs, + spi_sclk, + led_clk_o, + gain0_o, + gain1_o, + + otg_vbusoc); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [31:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + + inout iic_scl; + inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + input spi_sdi; + inout spi_sdo; + output spi_sclk; + output [ 1:0] spi_cs; + output led_clk_o; + output gain0_o; + output gain1_o; + + input otg_vbusoc; + + // internal signals + + wire [34:0] gpio_i; + wire [34:0] gpio_o; + wire [34:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire [23:0] offload_sdi_data; + + wire spi_sdo_o; + wire spi_sdo_t; + wire excitation; + + assign gain0_o = gpio_o[32]; + assign gain1_o = gpio_o[33]; + + assign gpio_i[34] = spi_sdi; // Interrupt + assign led_clk_o = excitation; + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_sdo_iobuf ( + .dt(spi_sdo_t), + .di(spi_sdo_o), + .dio(spi_sdo) + ); + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dt(gpio_t[31:0]), + .di(gpio_o[31:0]), + .do(gpio_i[31:0]), + .dio(gpio_bd) + ); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dt({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .di(iic_mux_scl_o_s), + .do(iic_mux_scl_i_s), + .dio(iic_mux_scl) + ); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dt({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .di(iic_mux_sda_o_s), + .do(iic_mux_sda_i_s), + .dio(iic_mux_sda) + ); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .spi_sdo (spi_sdo_o), + .spi_sdo_t (spi_sdo_t), + .spi_sdi (spi_sdi), + .spi_cs (spi_cs), + .spi_sclk (spi_sclk), + .excitation (excitation), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl index 59beb14d1..ea905c85a 100644 --- a/projects/scripts/adi_board.tcl +++ b/projects/scripts/adi_board.tcl @@ -25,12 +25,12 @@ proc ad_connect_type {p_name} { set m_name "" - if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]} if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]} - if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]} + if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]} if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]} - if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]} + if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]} if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]} + if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]} return $m_name }