axi_dmac: removed harmful SDC constraint
The set_false_path constraint targeted to the *ram* cells of the dmac matched several intra clock domain paths where the timing analysis got ignored resulting in intermitent data integrity issues.main
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ad05a5ecc1
commit
c42ed7dd52
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@ -4,7 +4,6 @@ set_false_path -to [get_registers *axi_dmac*cdc_sync_stage1*]
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set_false_path -from [get_registers *axi_dmac*cdc_sync_fifo_ram*]
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set_false_path -from [get_registers *axi_dmac*eot_mem*]
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set_false_path -to [get_registers *axi_dmac*reset_shift*]
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set_false_path -to [get_registers *axi_dmac*ram*]
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set_false_path -from [get_registers *axi_dmac*cdc_sync_stage2*] -to [get_registers *axi_dmac*up_rdata*]
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set_false_path -from [get_registers *axi_dmac*id*] -to [get_registers *axi_dmac*up_rdata*]
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set_false_path -from [get_registers *axi_dmac*address*] -to [get_registers *axi_dmac*up_rdata*]
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