From 7c3ed75b795b72c086901144dbdcba80d1cd71a3 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 8 Dec 2014 14:49:40 -0500 Subject: [PATCH 01/18] daq3: compilation fixes - latest changes --- projects/daq3/common/daq3_bd.tcl | 160 ++++++++++--------------------- 1 file changed, 50 insertions(+), 110 deletions(-) diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index 7c3ba78f5..59347bd53 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -63,11 +63,10 @@ if {$sys_zynq == 0} { set adc_dsync [create_bd_port -dir I adc_dsync] set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] -if {$sys_zynq == 1} { - - set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] - set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] -} + set axi_ad9152_dma_intr [create_bd_port -dir O axi_ad9152_dma_intr] + set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr] + set axi_daq3_spi_intr [create_bd_port -dir O axi_daq3_spi_intr ] + set axi_daq3_gpio_intr [create_bd_port -dir O axi_daq3_gpio_intr ] # dac peripherals @@ -118,11 +117,6 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma -if {$sys_zynq == 1} { - - p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 -} - if {$sys_zynq == 1} { set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] @@ -132,7 +126,8 @@ if {$sys_zynq == 1} { # dac/adc common gt/gpio set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt] - set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq3_gt + set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {4}] $axi_daq3_gt + set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {4}] $axi_daq3_gt set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_daq3_gt set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_daq3_gt set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_daq3_gt @@ -174,7 +169,6 @@ if {$sys_zynq == 0} { if {$sys_zynq == 0} { set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect - set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc } if {$sys_zynq == 1} { @@ -194,31 +188,6 @@ if {$sys_zynq == 1} { set_property LEFT 42 [get_bd_ports GPIO_T] } - # connections (pl ddr3) - -if {$sys_zynq == 1} { - - connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3] - connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk] -} - - # fmc dma clocks - -if {$sys_zynq == 1} { - - set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] - set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] - set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] - - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] - connect_bd_net -net sys_fmc_dma_async_reset \ - [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ - [get_bd_pins sys_ps7/FCLK_RESET2_N] - - connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source -} - # connections (spi and gpio) if {$sys_zynq == 0} { @@ -254,12 +223,6 @@ if {$sys_zynq == 0} { connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq3_gpio/gpio2_io_t] } -if {$sys_zynq == 0} { - - delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] - delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] -} - # connections (gt) connect_bd_net -net axi_daq3_gt_ref_clk_q [get_bd_pins axi_daq3_gt/ref_clk_q] [get_bd_ports rx_ref_clk] @@ -299,7 +262,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9152_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9152_dma/fifo_rd_en] connect_bd_net -net axi_ad9152_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9152_dma/fifo_rd_dout] connect_bd_net -net axi_ad9152_dac_dunf [get_bd_pins axi_ad9152_core/dac_dunf] [get_bd_pins axi_ad9152_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9152_dma_intr [get_bd_pins axi_ad9152_dma/irq] [get_bd_ports axi_ad9152_dma_intr] # connections (adc) @@ -321,29 +284,25 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_daq3_gt_rx_ip_data [get_bd_pins axi_daq3_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] connect_bd_net -net axi_daq3_gt_rx_data [get_bd_pins axi_daq3_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] -if {$sys_zynq == 1} { - - connect_bd_net -net axi_daq3_gt_rx_rst [get_bd_pins axi_ad9680_fifo/adc_rst] [get_bd_pins axi_daq3_gt/rx_rst] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_fifo/dma_rstn] $sys_fmc_dma_resetn_source - - connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_fifo/adc_clk] - connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_fifo/adc_wovf] connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] + + connect_bd_net -net axi_daq3_gt_rx_rst [get_bd_pins axi_ad9680_fifo/adc_rst] [get_bd_pins axi_daq3_gt/rx_rst] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_fifo/adc_clk] + connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_fifo/adc_wovf] connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_fifo/adc_wr] connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_fifo/adc_wdata] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/s_axis_aclk] - connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid] - connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/s_axis_aclk] + connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/s_axis_valid] connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data] - connect_bd_net -net axi_ad9680_xfer_req [get_bd_pins axi_ad9680_fifo/axi_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req] - connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] -} + connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready] + connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_fifo/dma_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr] # dac/adc clocks @@ -402,8 +361,8 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_spi/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gpio/s_axi_aresetn] - connect_bd_net -net axi_daq3_spi_irq [get_bd_pins axi_daq3_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] - connect_bd_net -net axi_daq3_gpio_irq [get_bd_pins axi_daq3_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] + connect_bd_net -net axi_daq3_spi_intr [get_bd_pins axi_daq3_spi/ip2intc_irpt] [get_bd_ports axi_daq3_spi_intr] + connect_bd_net -net axi_daq3_gpio_intr [get_bd_pins axi_daq3_gpio/ip2intc_irpt] [get_bd_ports axi_daq3_gpio_intr] } # gt uses hp3, and 100MHz clock for both DRP and AXI4 @@ -440,71 +399,53 @@ if {$sys_zynq == 0} { if {$sys_zynq == 0} { connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9152_dma/m_src_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn] connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] } else { connect_bd_intf_net -intf_net axi_ad9152_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9152_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] connect_bd_intf_net -intf_net axi_ad9152_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9152_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9152_dma/m_src_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn] connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] } # ila set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_jesd_rx_mon - connect_bd_net -net axi_daq3_gt_rx_mon_data [get_bd_pins axi_daq3_gt/rx_mon_data] - connect_bd_net -net axi_daq3_gt_rx_mon_trigger [get_bd_pins axi_daq3_gt/rx_mon_trigger] connect_bd_net -net axi_daq3_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_daq3_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] - connect_bd_net -net axi_daq3_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] - connect_bd_net -net axi_daq3_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] - - set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon - - connect_bd_net -net axi_daq3_gt_tx_mon_data [get_bd_pins axi_daq3_gt/tx_mon_data] - connect_bd_net -net axi_daq3_gt_tx_mon_trigger [get_bd_pins axi_daq3_gt/tx_mon_trigger] - connect_bd_net -net axi_daq3_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] - connect_bd_net -net axi_daq3_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] - connect_bd_net -net axi_daq3_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE0] # address map @@ -524,9 +465,9 @@ if {$sys_zynq == 0} { if {$sys_zynq == 0} { - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9152_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9152_dma/m_src_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl } else { @@ -534,6 +475,5 @@ if {$sys_zynq == 0} { create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm - create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr } From 8a72a6a0dc3f2535c78f4202ef14681b536fa514 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 8 Dec 2014 14:49:52 -0500 Subject: [PATCH 02/18] daq3: compilation fixes - latest changes --- projects/daq3/zc706/system_bd.tcl | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 229afce5b..401e1e9d9 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -1,5 +1,15 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl + +p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3] +connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk] +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] \ + [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr + source ../common/daq3_bd.tcl From abff7097f610e328f2f1021b8a5c03c10ce1e5f9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 8 Dec 2014 14:50:03 -0500 Subject: [PATCH 03/18] daq3: compilation fixes - latest changes --- projects/daq3/zc706/system_top.v | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index df5d131ed..4d6983bf1 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -116,6 +116,7 @@ module system_top ( trig_p, trig_n, + adc_fdb, adc_fda, dac_irq, @@ -208,6 +209,7 @@ module system_top ( input trig_p; input trig_n; + inout adc_fdb; inout adc_fda; inout dac_irq; @@ -236,11 +238,11 @@ module system_top ( // internal signals + wire sysref; + wire trig; wire [42:0] gpio_i; wire [42:0] gpio_o; wire [42:0] gpio_t; - wire sysref; - wire trig; wire rx_ref_clk; wire rx_sysref; wire rx_sync; @@ -263,6 +265,7 @@ module system_top ( wire adc_enable_1; wire adc_valid_0; wire adc_valid_1; + wire [15:0] ps_intrs; // adc-dac data @@ -503,6 +506,22 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), + .ps_intr_0 (ps_intrs[0]), + .ps_intr_1 (ps_intrs[1]), + .ps_intr_10 (ps_intrs[10]), + .ps_intr_11 (ps_intrs[11]), + .ps_intr_12 (ps_intrs[12]), + .ps_intr_13 (ps_intrs[13]), + .ps_intr_2 (ps_intrs[2]), + .ps_intr_3 (ps_intrs[3]), + .ps_intr_4 (ps_intrs[4]), + .ps_intr_5 (ps_intrs[5]), + .ps_intr_6 (ps_intrs[6]), + .ps_intr_7 (ps_intrs[7]), + .ps_intr_8 (ps_intrs[8]), + .ps_intr_9 (ps_intrs[9]), + .axi_ad9152_dma_intr (ps_intrs[12]), + .axi_ad9680_dma_intr (ps_intrs[13]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From 6aad2fbbb2f28d2283994920f818db4684fa526b Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 9 Dec 2014 09:56:14 +0200 Subject: [PATCH 04/18] axi_hdmi_tx: Fixed typo in altera related core --- library/axi_hdmi_tx/axi_hdmi_tx_alt.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_alt.v b/library/axi_hdmi_tx/axi_hdmi_tx_alt.v index d911c01fe..c9e60a63c 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_alt.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_alt.v @@ -218,7 +218,7 @@ module axi_hdmi_tx_alt ( .PCORE_Cr_Cb_N (PCORE_Cr_Cb_N), .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), .PCORE_EMBEDDED_SYNC (PCORE_EMBEDDED_SYNC), - .C_S_AXI_MIN_SIZE (32'hffff) + .C_S_AXI_MIN_SIZE (32'hffff)) i_hdmi_tx ( .hdmi_clk (hdmi_clk), .hdmi_out_clk (hdmi_out_clk), From ee04eb637b2e74dd1ebe07fd12debf8883b56f77 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 9 Dec 2014 11:48:46 +0200 Subject: [PATCH 05/18] ad9467_kc705: Fix interrupts --- projects/ad9467_fmc/kc705/system_top.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/ad9467_fmc/kc705/system_top.v b/projects/ad9467_fmc/kc705/system_top.v index 6a5b5841a..fb6006799 100644 --- a/projects/ad9467_fmc/kc705/system_top.v +++ b/projects/ad9467_fmc/kc705/system_top.v @@ -244,8 +244,8 @@ system_wrapper i_system_wrapper ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9467_dma_irq (mb_intr_13), - .ad9467_spi_irq (mb_intr_10), + .ad9467_dma_irq (mb_intr[10]), + .ad9467_spi_irq (mb_intr[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), From 915ee7a268523a6ee736e0142328eda43495169e Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 9 Dec 2014 11:51:36 +0200 Subject: [PATCH 06/18] fmcjesdadc1_kc705: Connect the SPI interrupt to the controller --- projects/fmcjesdadc1/kc705/system_top.v | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v index f45bc4a7e..b3ffb4f5f 100644 --- a/projects/fmcjesdadc1/kc705/system_top.v +++ b/projects/fmcjesdadc1/kc705/system_top.v @@ -371,6 +371,7 @@ module system_top ( .mb_intr_31 (mb_intrs[31]), .ad9250_0_dma_intr (mb_intrs[10]), .ad9250_1_dma_intr (mb_intrs[11]), + .ad9250_spi_intr (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), From a0d5e7862e2f9c3b0c075feda7d2f302ddbb63d3 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 9 Dec 2014 12:07:49 +0200 Subject: [PATCH 07/18] ad9467_kc705: Fix typos. --- projects/ad9467_fmc/kc705/system_top.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/ad9467_fmc/kc705/system_top.v b/projects/ad9467_fmc/kc705/system_top.v index fb6006799..ba068e01a 100644 --- a/projects/ad9467_fmc/kc705/system_top.v +++ b/projects/ad9467_fmc/kc705/system_top.v @@ -244,8 +244,8 @@ system_wrapper i_system_wrapper ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9467_dma_irq (mb_intr[10]), - .ad9467_spi_irq (mb_intr[13]), + .ad9467_dma_irq (mb_intrs[10]), + .ad9467_spi_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), From c4152627f0ec13cc789922a2722355a5e19daef3 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 9 Dec 2014 13:59:19 +0200 Subject: [PATCH 08/18] plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long, it needs to be just one adc_clk cycle. --- library/axi_fifo2s/axi_fifo2s_adc.v | 67 +++++++++++++++-------------- 1 file changed, 34 insertions(+), 33 deletions(-) diff --git a/library/axi_fifo2s/axi_fifo2s_adc.v b/library/axi_fifo2s/axi_fifo2s_adc.v index ffc236159..4677d1db9 100644 --- a/library/axi_fifo2s/axi_fifo2s_adc.v +++ b/library/axi_fifo2s/axi_fifo2s_adc.v @@ -81,10 +81,10 @@ module axi_fifo2s_adc ( // internal registers - reg adc_wovf = 'd0; - reg [ 2:0] adc_wcnt_int = 'd0; - reg adc_dwr = 'd0; - reg [AXI_DATA_WIDTH-1:0] adc_ddata = 'd0; + reg adc_wovf = 'd0; + reg [ 2:0] adc_wcnt_int = 'd0; + reg adc_dwr = 'd0; + reg [AXI_DATA_WIDTH-1:0] adc_ddata = 'd0; // internal signals @@ -100,35 +100,36 @@ module axi_fifo2s_adc ( adc_ddata <= 'd0; end else begin adc_wovf <= | adc_xfer_status_s; - adc_wcnt_int <= adc_wcnt_int + 1'b1; - case (ADC_MEM_RATIO) - 8: begin - adc_dwr <= adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2]; - adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata; - adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <= - adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)]; - end - 4: begin - adc_dwr <= adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1]; - adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata; - adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <= - adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)]; - end - 2: begin - adc_dwr <= adc_wr & adc_wcnt_int[0]; - adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata; - adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <= - adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)]; - end - 1: begin - adc_dwr <= adc_wr; - adc_ddata <= adc_wdata; - end - default: begin - adc_dwr <= 'd0; - adc_ddata <= 'd0; - end - endcase + adc_dwr <= (ADC_MEM_RATIO == 8) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2] : + (ADC_MEM_RATIO == 4) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] : + (ADC_MEM_RATIO == 2) ? adc_wr & adc_wcnt_int[0] : + (ADC_MEM_RATIO == 1) ? adc_wr : 'd0; + if (adc_wr == 1'b1) begin + adc_wcnt_int <= adc_wcnt_int + 1'b1; + case (ADC_MEM_RATIO) + 8: begin + adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata; + adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <= + adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)]; + end + 4: begin + adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata; + adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <= + adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)]; + end + 2: begin + adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata; + adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <= + adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)]; + end + 1: begin + adc_ddata <= adc_wdata; + end + default: begin + adc_ddata <= 'd0; + end + endcase + end end end From 2e4640d5c5c952a7de81aa430570a28c69a91dba Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 9 Dec 2014 16:17:46 +0200 Subject: [PATCH 09/18] ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl --- projects/ad9467_fmc/common/ad9467_bd.tcl | 2 +- projects/common/kc705/kc705_system_bd.tcl | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index 7a04f1008..d8069bac5 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -222,7 +222,7 @@ if {$sys_zynq == 0} { } if {$sys_zynq == 0} { - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9467_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9467_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl } else { create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9467_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm } diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index f1f5fe707..c42d589ca 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -439,8 +439,8 @@ create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [g create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma -create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_instr_ddr_cntrl +create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr +create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_instr_ddr_cntrl create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl From a2607a8057e12d06fec2ee0f8afe3df34de8f25a Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 9 Dec 2014 10:37:12 -0500 Subject: [PATCH 10/18] fmcadc4: fifo updates --- projects/fmcadc4/common/fmcadc4_bd.tcl | 120 +++++++++++-------------- 1 file changed, 53 insertions(+), 67 deletions(-) diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index b9c3f2612..2b1aa1eef 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -1,17 +1,17 @@ # fmcadc4 -if {$sys_zynq == 0} { +if {$sys_zynq == 1} { - set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] - set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o] + set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o] + set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o] + set spi_csn_i [create_bd_port -dir I spi_csn_i] } else { - set spi_csn_0 [create_bd_port -dir O spi_csn_0] - set spi_csn_1 [create_bd_port -dir O spi_csn_1] - set spi_csn_2 [create_bd_port -dir O spi_csn_2] - set spi_csn_i [create_bd_port -dir I spi_csn_i] + set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] } set spi_clk_i [create_bd_port -dir I spi_clk_i] @@ -56,9 +56,9 @@ if {$sys_zynq == 0} { set adc_dsync [create_bd_port -dir I adc_dsync] set adc_ddata [create_bd_port -dir I -from 255 -to 0 adc_ddata] + set fmcadc4_dma_intr [create_bd_port -dir O fmcadc4_dma_intr] set fmcadc4_spi_intr [create_bd_port -dir O fmcadc4_spi_intr] set fmcadc4_gpio_intr [create_bd_port -dir O fmcadc4_gpio_intr] - set fmcadc4_dma_intr [create_bd_port -dir O fmcadc4_dma_intr] # adc peripherals @@ -70,17 +70,18 @@ if {$sys_zynq == 0} { set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9234_jesd set axi_ad9234_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9234_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9234_dma set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9234_dma set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9234_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9234_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9234_dma set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9234_dma set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9234_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9234_dma set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9234_dma if {$sys_zynq == 1} { @@ -91,7 +92,7 @@ if {$sys_zynq == 1} { # dac/adc common gt/gpio set axi_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc4_gt] - set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_fmcadc4_gt + set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_fmcadc4_gt if {$sys_zynq == 1} { @@ -161,15 +162,15 @@ if {$sys_zynq == 0} { } else { - connect_bd_net -net spi_csn_0 [get_bd_ports spi_csn_0] [get_bd_pins sys_ps7/SPI0_SS_O] - connect_bd_net -net spi_csn_1 [get_bd_ports spi_csn_1] [get_bd_pins sys_ps7/SPI0_SS1_O] - connect_bd_net -net spi_csn_2 [get_bd_ports spi_csn_2] [get_bd_pins sys_ps7/SPI0_SS2_O] - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + connect_bd_net -net spi_csn_2_o [get_bd_ports spi_csn_2_o] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] } if {$sys_zynq == 0} { @@ -212,24 +213,33 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_fmcadc4_gt_rx_data [get_bd_pins axi_fmcadc4_gt/rx_data] [get_bd_ports gt_data] connect_bd_net -net axi_fmcadc4_gt_0_rx_data [get_bd_pins axi_ad9234_core_0/rx_data] [get_bd_ports gt_data_0] connect_bd_net -net axi_fmcadc4_gt_1_rx_data [get_bd_pins axi_ad9234_core_1/rx_data] [get_bd_ports gt_data_1] - connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk] + connect_bd_net -net axi_ad9234_0_adc_enable_0 [get_bd_pins axi_ad9234_core_0/adc_enable_0] [get_bd_ports adc_enable_0] connect_bd_net -net axi_ad9234_0_adc_valid_0 [get_bd_pins axi_ad9234_core_0/adc_valid_0] [get_bd_ports adc_valid_0] connect_bd_net -net axi_ad9234_0_adc_data_0 [get_bd_pins axi_ad9234_core_0/adc_data_0] [get_bd_ports adc_data_0] connect_bd_net -net axi_ad9234_0_adc_enable_1 [get_bd_pins axi_ad9234_core_0/adc_enable_1] [get_bd_ports adc_enable_1] connect_bd_net -net axi_ad9234_0_adc_valid_1 [get_bd_pins axi_ad9234_core_0/adc_valid_1] [get_bd_ports adc_valid_1] connect_bd_net -net axi_ad9234_0_adc_data_1 [get_bd_pins axi_ad9234_core_0/adc_data_1] [get_bd_ports adc_data_1] + connect_bd_net -net axi_ad9234_1_adc_enable_0 [get_bd_pins axi_ad9234_core_1/adc_enable_0] [get_bd_ports adc_enable_2] connect_bd_net -net axi_ad9234_1_adc_valid_0 [get_bd_pins axi_ad9234_core_1/adc_valid_0] [get_bd_ports adc_valid_2] connect_bd_net -net axi_ad9234_1_adc_data_0 [get_bd_pins axi_ad9234_core_1/adc_data_0] [get_bd_ports adc_data_2] connect_bd_net -net axi_ad9234_1_adc_enable_1 [get_bd_pins axi_ad9234_core_1/adc_enable_1] [get_bd_ports adc_enable_3] connect_bd_net -net axi_ad9234_1_adc_valid_1 [get_bd_pins axi_ad9234_core_1/adc_valid_1] [get_bd_ports adc_valid_3] connect_bd_net -net axi_ad9234_1_adc_data_1 [get_bd_pins axi_ad9234_core_1/adc_data_1] [get_bd_ports adc_data_3] - connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9234_dma/fifo_wr_en] - connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync] - connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9234_dma/fifo_wr_din] - connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9234_dma_irq [get_bd_pins axi_ad9234_dma/irq] [get_bd_ports fmcadc4_dma_intr] + + connect_bd_net -net axi_fmcadc4_gt_rx_rst [get_bd_pins axi_ad9234_fifo/adc_rst] [get_bd_pins axi_fmcadc4_gt/rx_rst] + connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins axi_ad9234_fifo/adc_clk] + connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins axi_ad9234_fifo/adc_wovf] + connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9234_fifo/adc_wr] + connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9234_fifo/adc_wdata] + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_fifo/dma_clk] [get_bd_pins axi_ad9234_dma/s_axis_aclk] + connect_bd_net -net axi_ad9234_dma_dvalid [get_bd_pins axi_ad9234_fifo/dma_wr] [get_bd_pins axi_ad9234_dma/s_axis_valid] + connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins axi_ad9234_fifo/dma_wdata] [get_bd_pins axi_ad9234_dma/s_axis_data] + connect_bd_net -net axi_ad9234_dma_dready [get_bd_pins axi_ad9234_fifo/dma_wready] [get_bd_pins axi_ad9234_dma/s_axis_ready] + connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins axi_ad9234_fifo/dma_xfer_req] [get_bd_pins axi_ad9234_dma/s_axis_xfer_req] + connect_bd_net -net fmcadc4_dma_intr [get_bd_pins axi_ad9234_dma/irq] [get_bd_ports fmcadc4_dma_intr] # dac/adc clocks @@ -310,64 +320,40 @@ if {$sys_zynq == 0} { # memory interconnects share the same clock (fclk2) -if {$sys_zynq == 1} { - set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] - - set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] - set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] - - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] - connect_bd_net -net sys_fmc_dma_async_reset \ - [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ - [get_bd_pins sys_ps7/FCLK_RESET2_N] - - connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source -} - # interconnect (mem/dac) if {$sys_zynq == 0} { connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] } else { connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] } # ila set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {256}] $ila_jesd_rx_mon - connect_bd_net -net axi_fmcadc4_gt_rx_mon_data [get_bd_pins axi_fmcadc4_gt/rx_mon_data] - connect_bd_net -net axi_fmcadc4_gt_rx_mon_trigger [get_bd_pins axi_fmcadc4_gt/rx_mon_trigger] connect_bd_net -net axi_fmcadc4_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_fmcadc4_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] - connect_bd_net -net axi_fmcadc4_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] - connect_bd_net -net axi_fmcadc4_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] - connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE0] # address map From e2a9502e1ed1290741c1abcb9f0aac5b5217af22 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 9 Dec 2014 10:37:22 -0500 Subject: [PATCH 11/18] fmcadc4: fifo updates --- projects/fmcadc4/zc706/system_bd.tcl | 67 +++++----------------------- 1 file changed, 10 insertions(+), 57 deletions(-) diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 61c9b6a2d..06d15fdab 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -1,62 +1,15 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl + +p_plddr3_fifo [current_bd_instance .] axi_ad9234_fifo 256 + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9234_fifo/DDR3] +connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9234_fifo/sys_clk] +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9234_fifo/axi_fifo2s/axi] \ + [get_bd_addr_segs axi_ad9234_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr + source ../common/fmcadc4_bd.tcl -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9234_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9234_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9234_dma - -p_plddr3_fifo [current_bd_instance .] plddr3_fifo 256 - -set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] -set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] - -connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3] -connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] - -delete_bd_objs [get_bd_nets axi_ad9234_adc_clk] -delete_bd_objs [get_bd_nets axi_ad9234_adc_dwr] -delete_bd_objs [get_bd_nets axi_ad9234_adc_ddata] -delete_bd_objs [get_bd_nets axi_ad9234_adc_dsync] -delete_bd_objs [get_bd_nets axi_ad9234_adc_dovf] - -connect_bd_net -net [get_bd_nets axi_fmcadc4_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_fmcadc4_gt/rx_rst] -connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] -connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins axi_ad9234_dma/s_axis_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] - -connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] -connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] -connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] -connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] - -connect_bd_net -net sys_100m_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9234_dma/s_axis_aclk] -connect_bd_net -net axi_ad9234_dma_ready [get_bd_pins plddr3_fifo/dma_wready] [get_bd_pins axi_ad9234_dma/s_axis_ready] -connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins axi_ad9234_dma/s_axis_valid] [get_bd_pins plddr3_fifo/dma_wvalid] -connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins axi_ad9234_dma/s_axis_data] [get_bd_pins plddr3_fifo/dma_wdata] - -connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk] -connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - -connect_bd_net -net axi_ad9234_dma_irq [get_bd_ports fmcadc4_dma_intr] [get_bd_pins sys_concat_intc/In2] - -set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon -set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_dma_mon - -connect_bd_net -net sys_100m_clk [get_bd_pins ila_dma_mon/clk] -connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins ila_dma_mon/probe0] -connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] -connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins ila_dma_mon/probe2] -connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status] -connect_bd_net -net axi_ad9234_dma_ready [get_bd_pins ila_dma_mon/probe4] -connect_bd_net -net axi_ad9234_adc_dwr [get_bd_pins ila_jesd_rx_mon/probe4] - - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr - From f044ab94e05ffb008d1a0343ef2c5dcbd45d0240 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 9 Dec 2014 10:37:33 -0500 Subject: [PATCH 12/18] fmcadc4: fifo updates --- projects/fmcadc4/zc706/system_constr.xdc | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcadc4/zc706/system_constr.xdc b/projects/fmcadc4/zc706/system_constr.xdc index 04f47ffff..49aa12be9 100644 --- a/projects/fmcadc4/zc706/system_constr.xdc +++ b/projects/fmcadc4/zc706/system_constr.xdc @@ -47,12 +47,4 @@ set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9234_2 create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcadc4_gt_rx_clk] -create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] -create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] -create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] - -set_clock_groups -asynchronous -group {rx_div_clk} -set_clock_groups -asynchronous -group {fmc_dma_clk} -set_clock_groups -asynchronous -group {pl_ddr_clk} -set_clock_groups -asynchronous -group {pl_dma_clk} From 0c6cbdd303a467cc147e2468c007f1d416d0ce58 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 9 Dec 2014 10:37:43 -0500 Subject: [PATCH 13/18] fmcadc4: fifo updates --- projects/fmcadc4/zc706/system_top.v | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/projects/fmcadc4/zc706/system_top.v b/projects/fmcadc4/zc706/system_top.v index c7409b366..8496a20ef 100644 --- a/projects/fmcadc4/zc706/system_top.v +++ b/projects/fmcadc4/zc706/system_top.v @@ -238,6 +238,7 @@ module system_top ( wire adc_valid_2; wire adc_valid_3; wire [255:0] gt_data; + wire [15:0] ps_intrs; wire [ 6:0] csn; wire [ 2:0] csn_i; @@ -518,6 +519,21 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), + .ps_intr_0 (ps_intrs[0]), + .ps_intr_1 (ps_intrs[1]), + .ps_intr_10 (ps_intrs[10]), + .ps_intr_11 (ps_intrs[11]), + .ps_intr_12 (ps_intrs[12]), + .ps_intr_13 (ps_intrs[13]), + .ps_intr_2 (ps_intrs[2]), + .ps_intr_3 (ps_intrs[3]), + .ps_intr_4 (ps_intrs[4]), + .ps_intr_5 (ps_intrs[5]), + .ps_intr_6 (ps_intrs[6]), + .ps_intr_7 (ps_intrs[7]), + .ps_intr_8 (ps_intrs[8]), + .ps_intr_9 (ps_intrs[9]), + .fmcadc4_dma_intr (ps_intrs[12]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), @@ -526,10 +542,10 @@ module system_top ( .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), - .spi_csn_0 (csn_i[0]), - .spi_csn_1 (csn_i[1]), - .spi_csn_2 (csn_i[2]), .spi_csn_i (1'b1), + .spi_csn_0_o (csn_i[0]), + .spi_csn_1_o (csn_i[1]), + .spi_csn_2_o (csn_i[2]), .spi_sdi_i (spi_miso), .spi_sdo_i (spi_mosi), .spi_sdo_o (spi_mosi), From 138e789fb6a6712fb63eabbf12c935f88f1a68de Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 9 Dec 2014 17:38:16 +0100 Subject: [PATCH 14/18] projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl: Fix interrupts sys_concat_intc: don't reset NUM_PORTS to 6 Signed-off-by: Michael Hennerich --- projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 6 ------ 1 file changed, 6 deletions(-) diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index 18ae5155a..d8ab40fff 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -131,12 +131,6 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect - set_property -dict [list CONFIG.NUM_PORTS {6}] $sys_concat_intc - - delete_bd_objs [get_bd_nets sys_concat_intc_din_2] - delete_bd_objs [get_bd_ports unc_int2] - delete_bd_objs [get_bd_nets sys_concat_intc_din_3] - delete_bd_objs [get_bd_ports unc_int3] } # connections (spi and gpio) From d57b6b01c68a3e34485e0cff5d7d38d302ab00ce Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 9 Dec 2014 14:28:11 -0500 Subject: [PATCH 15/18] fmcomms2/ml605: compilation fixes --- projects/fmcomms2/ml605/system_project.tcl | 25 +++++++++++++--------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/projects/fmcomms2/ml605/system_project.tcl b/projects/fmcomms2/ml605/system_project.tcl index cedd09c65..1b4999746 100644 --- a/projects/fmcomms2/ml605/system_project.tcl +++ b/projects/fmcomms2/ml605/system_project.tcl @@ -5,7 +5,11 @@ source $ad_hdl_dir/projects/scripts/adi_project.tcl adi_project_create fmcomms2_ml605 adi_project_files fmcomms2_ml605 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_mul_u16.v" \ + "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ + "$ad_hdl_dir/library/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ @@ -22,20 +26,19 @@ adi_project_files fmcomms2_ml605 [list \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ "$ad_hdl_dir/library/common/up_dac_common.v" \ "$ad_hdl_dir/library/common/up_dac_channel.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_dev_if.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_pnlb.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx_pnmon.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx_channel.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx_dds.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx_channel.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx.v" \ - "$ad_hdl_dir/library/axi_ad9361/axi_ad9361.v" \ "$ad_hdl_dir/library/common/sync_bits.v" \ "$ad_hdl_dir/library/common/sync_gray.v" \ "$ad_hdl_dir/library/axi_fifo/axi_fifo.v" \ "$ad_hdl_dir/library/axi_fifo/address_gray.v" \ "$ad_hdl_dir/library/axi_fifo/address_gray_pipelined.v" \ + "$ad_hdl_dir/library/axi_fifo/address_sync.v" \ + "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_dev_if.v" \ + "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx_pnmon.v" \ + "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx_channel.v" \ + "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx.v" \ + "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx_channel.v" \ + "$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx.v" \ + "$ad_hdl_dir/library/axi_ad9361/axi_ad9361.v" \ "$ad_hdl_dir/library/axi_dmac/address_generator.v" \ "$ad_hdl_dir/library/axi_dmac/data_mover.v" \ "$ad_hdl_dir/library/axi_dmac/request_arb.v" \ @@ -53,6 +56,8 @@ adi_project_files fmcomms2_ml605 [list \ "$ad_hdl_dir/library/axi_dmac/response_generator.v" \ "$ad_hdl_dir/library/axi_dmac/axi_dmac.v" \ "$ad_hdl_dir/library/axi_dmac/axi_repack.v" \ + "$ad_hdl_dir/library/util_adc_pack/util_adc_pack.v" \ + "$ad_hdl_dir/library/util_dac_unpack/util_dac_unpack.v" \ "system_constr.ucf" \ "system_top.v" ] From d7a6b5e6d025c36bef400b80db9f12c78e463728 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 9 Dec 2014 14:28:22 -0500 Subject: [PATCH 16/18] fmcomms2/ml605: compilation fixes --- projects/fmcomms2/ml605/system_top.v | 140 +++++++++++++++++++++++---- 1 file changed, 119 insertions(+), 21 deletions(-) diff --git a/projects/fmcomms2/ml605/system_top.v b/projects/fmcomms2/ml605/system_top.v index 58206fdc4..117a0776e 100644 --- a/projects/fmcomms2/ml605/system_top.v +++ b/projects/fmcomms2/ml605/system_top.v @@ -312,6 +312,30 @@ module system_top ( wire axi_dev_rx_axil_rready; wire sys_200m_clk; wire clk; + wire adc_enable_i0; + wire adc_valid_i0; + wire [ 15:0] adc_data_i0; + wire adc_enable_q0; + wire adc_valid_q0; + wire [ 15:0] adc_data_q0; + wire adc_enable_i1; + wire adc_valid_i1; + wire [ 15:0] adc_data_i1; + wire adc_enable_q1; + wire adc_valid_q1; + wire [ 15:0] adc_data_q1; + wire dac_enable_i0; + wire dac_valid_i0; + wire [ 15:0] dac_data_i0; + wire dac_enable_q0; + wire dac_valid_q0; + wire [ 15:0] dac_data_q0; + wire dac_enable_i1; + wire dac_valid_i1; + wire [ 15:0] dac_data_i1; + wire dac_enable_q1; + wire dac_valid_q1; + wire [ 15:0] dac_data_q1; wire adc_dwr; wire [ 63:0] adc_ddata; wire adc_dsync; @@ -379,36 +403,50 @@ module system_top ( // instantiations - axi_ad9361 #( - .PCORE_BUFTYPE (1), - .C_BASEADDR (32'h00000000), - .C_HIGHADDR (32'hffffffff)) - i_axi_ad9361 ( + axi_ad9361 #(.PCORE_DEVICE_TYPE (1)) i_axi_ad9361 ( .rx_clk_in_p (rx_clk_in_p), .rx_clk_in_n (rx_clk_in_n), .rx_frame_in_p (rx_frame_in_p), .rx_frame_in_n (rx_frame_in_n), .rx_data_in_p (rx_data_in_p), .rx_data_in_n (rx_data_in_n), - .adc_start_in (1'd0), - .adc_start_out (), .tx_clk_out_p (tx_clk_out_p), .tx_clk_out_n (tx_clk_out_n), .tx_frame_out_p (tx_frame_out_p), .tx_frame_out_n (tx_frame_out_n), .tx_data_out_p (tx_data_out_p), .tx_data_out_n (tx_data_out_n), - .dac_enable_in (1'd0), - .dac_enable_out (), + .dac_sync_in (1'd0), + .dac_sync_out (), .delay_clk (sys_200m_clk), + .l_clk (clk), .clk (clk), - .adc_dwr (adc_dwr), - .adc_ddata (adc_ddata), - .adc_dsync (adc_dsync), + .adc_enable_i0 (adc_enable_i0), + .adc_valid_i0 (adc_valid_i0), + .adc_data_i0 (adc_data_i0), + .adc_enable_q0 (adc_enable_q0), + .adc_valid_q0 (adc_valid_q0), + .adc_data_q0 (adc_data_q0), + .adc_enable_i1 (adc_enable_i1), + .adc_valid_i1 (adc_valid_i1), + .adc_data_i1 (adc_data_i1), + .adc_enable_q1 (adc_enable_q1), + .adc_valid_q1 (adc_valid_q1), + .adc_data_q1 (adc_data_q1), .adc_dovf (adc_dovf), - .adc_dunf (1'd0), - .dac_drd (dac_drd), - .dac_ddata (dac_ddata), + .adc_dunf (1'b0), + .dac_enable_i0 (dac_enable_i0), + .dac_valid_i0 (dac_valid_i0), + .dac_data_i0 (dac_data_i0), + .dac_enable_q0 (dac_enable_q0), + .dac_valid_q0 (dac_valid_q0), + .dac_data_q0 (dac_data_q0), + .dac_enable_i1 (dac_enable_i1), + .dac_valid_i1 (dac_valid_i1), + .dac_data_i1 (dac_data_i1), + .dac_enable_q1 (dac_enable_q1), + .dac_valid_q1 (dac_valid_q1), + .dac_data_q1 (dac_data_q1), .dac_dovf (1'd0), .dac_dunf (dac_dunf), .s_axi_aclk (axi_dev_tx_axil_aclk), @@ -430,12 +468,44 @@ module system_top ( .s_axi_rdata (axi_dev_tx_axil_rdata), .s_axi_rresp (axi_dev_tx_axil_rresp), .s_axi_rready (axi_dev_tx_axil_rready), - .adc_mon_valid (), - .adc_mon_data ()); + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .dev_dbg_data (), + .dev_l_dbg_data ()); + + util_dac_unpack #(.CHANNELS (4)) i_unpack_tx ( + .clk (clk), + .dac_enable_00 (dac_enable_i0), + .dac_valid_00 (dac_valid_i0), + .dac_data_00 (dac_data_i0), + .dac_enable_01 (dac_enable_q0), + .dac_valid_01 (dac_valid_q0), + .dac_data_01 (dac_data_q0), + .dac_enable_02 (dac_enable_i1), + .dac_valid_02 (dac_valid_i1), + .dac_data_02 (dac_data_i1), + .dac_enable_03 (dac_enable_q1), + .dac_valid_03 (dac_valid_q1), + .dac_data_03 (dac_data_q1), + .dac_enable_04 (1'd0), + .dac_valid_04 (1'd0), + .dac_data_04 (), + .dac_enable_05 (1'd0), + .dac_valid_05 (1'd0), + .dac_data_05 (), + .dac_enable_06 (1'd0), + .dac_valid_06 (1'd0), + .dac_data_06 (), + .dac_enable_07 (1'd0), + .dac_valid_07 (1'd0), + .dac_data_07 (), + .fifo_valid (dac_drd), + .dma_rd (dac_drd), + .dma_data (dac_ddata)); axi_dmac #( - .C_BASEADDR (32'h00000000), - .C_HIGHADDR (32'hffffffff), .C_DMA_TYPE_SRC (0), .C_DMA_TYPE_DEST (2), .C_CYCLIC (1), @@ -519,9 +589,37 @@ module system_top ( .fifo_rd_dout (dac_ddata), .fifo_rd_underflow (dac_dunf)); + util_adc_pack #(.CHANNELS (4)) i_pack_rx ( + .clk (clk), + .chan_enable_0 (adc_enable_i0), + .chan_valid_0 (adc_valid_i0), + .chan_data_0 (adc_data_i0), + .chan_enable_1 (adc_enable_q0), + .chan_valid_1 (adc_valid_q0), + .chan_data_1 (adc_data_q0), + .chan_enable_2 (adc_enable_i1), + .chan_valid_2 (adc_valid_i1), + .chan_data_2 (adc_data_i1), + .chan_enable_3 (adc_enable_q1), + .chan_valid_3 (adc_valid_q1), + .chan_data_3 (adc_data_q1), + .chan_enable_4 (1'd0), + .chan_valid_4 (1'd0), + .chan_data_4 (16'd0), + .chan_enable_5 (1'd0), + .chan_valid_5 (1'd0), + .chan_data_5 (16'd0), + .chan_enable_6 (1'd0), + .chan_valid_6 (1'd0), + .chan_data_6 (16'd0), + .chan_enable_7 (1'd0), + .chan_valid_7 (1'd0), + .chan_data_7 (16'd0), + .ddata (adc_ddata), + .dvalid (adc_dwr), + .dsync (adc_dsync)); + axi_dmac #( - .C_BASEADDR (32'h00000000), - .C_HIGHADDR (32'hffffffff), .C_DMA_TYPE_SRC (2), .C_DMA_TYPE_DEST (0), .C_CYCLIC (0), From 842ba19aaaf40dfd45188a4a68e8e7d063e9690c Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 9 Dec 2014 14:29:38 -0500 Subject: [PATCH 17/18] fmcomms2/ml605: compilation fixes --- projects/common/ml605/data/system.ncf | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 projects/common/ml605/data/system.ncf diff --git a/projects/common/ml605/data/system.ncf b/projects/common/ml605/data/system.ncf old mode 100644 new mode 100755 From 9e8fd8ed9e9e29eed8b1dea9db46b07cb814eca0 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 11 Dec 2014 11:13:07 +0200 Subject: [PATCH 18/18] base_design: External IIC reset is connected to Vcc External IIC reset is connected to Vcc in case of AC701, KC705 and VC707 --- projects/common/ac701/ac701_system_bd.tcl | 2 +- projects/common/kc705/kc705_system_bd.tcl | 2 +- projects/common/vc707/vc707_system_bd.tcl | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 76f515f33..3be137cb8 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -367,7 +367,7 @@ connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [ge connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio] connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2] -connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo] +connect_bd_net -net sys_const_vcc_vcc [get_bd_ports iic_rstn] [get_bd_pins sys_const_vcc/dout] connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] # hdmi peripherals diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index c42d589ca..f6135f293 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -334,7 +334,7 @@ connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [ge connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio] connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2] -connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo] +connect_bd_net -net sys_const_vcc_vcc [get_bd_ports iic_rstn] [get_bd_pins sys_const_vcc/dout] connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] # hdmi diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index f4d397d29..ed364cf03 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -164,6 +164,7 @@ set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dm set axi_linear_flash [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_emc:3.0 axi_linear_flash] set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.EMC_BOARD_INTERFACE {linear_flash}] $axi_linear_flash +set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 sys_const_vcc] # connections @@ -365,7 +366,7 @@ connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [ge connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio] connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2] -connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo] +connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/dout] [get_bd_ports iic_rstn] connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] # hdmi peripherals