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fmcadc5: update adcfifo/dacfifo

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Laszlo Nagy 2019-01-22 13:20:34 +00:00 committed by Laszlo Nagy
parent 4ec1204767
commit c37b24d00f
2 changed files with 6 additions and 3 deletions
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6
projects/fmcadc5/common/fmcadc5_bd.tcl
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@ -2,6 +2,10 @@
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name axi_ad9625_fifo
set adc_data_width 512
set adc_dma_data_width 64
# adc peripherals # adc peripherals
ad_ip_instance util_adxcvr util_fmcadc5_0_xcvr ad_ip_instance util_adxcvr util_fmcadc5_0_xcvr
@ -69,6 +73,8 @@ ad_ip_parameter axi_ad9625_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_SRC 64 ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
# reference clocks & resets # reference clocks & resets
create_bd_port -dir I rx_ref_clk_0 create_bd_port -dir I rx_ref_clk_0

3
projects/fmcadc5/vc707/system_bd.tcl
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@ -1,9 +1,6 @@
## FIFO depth is 16Mb - 1M Samples ## FIFO depth is 16Mb - 1M Samples
set adc_fifo_name axi_ad9625_fifo
set adc_fifo_address_width 18 set adc_fifo_address_width 18
set adc_data_width 512
set adc_dma_data_width 64
## NOTE: With this configuration the #36Kb BRAM utilization is at ~70% ## NOTE: With this configuration the #36Kb BRAM utilization is at ~70%