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daq3: vivado build

main
Rejeesh Kutty 2014-10-06 10:33:28 -04:00
parent d47776a4a0
commit c375b5b26e
12 changed files with 371 additions and 547 deletions
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156
library/axi_ad9152/axi_ad9152.v
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@ -39,7 +39,7 @@
`timescale 1ns/100ps
module axi_ad9144 (
module axi_ad9152 (
// jesd interface
// tx_clk is (line-rate/40)
@ -56,12 +56,6 @@ module axi_ad9144 (
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_valid_2,
dac_enable_2,
dac_ddata_2,
dac_valid_3,
dac_enable_3,
dac_ddata_3,
dac_dovf,
dac_dunf,
@ -90,104 +84,84 @@ module axi_ad9144 (
// parameters
parameter PCORE_ID = 0;
parameter PCORE_QUAD_DUAL_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [(128*PCORE_QUAD_DUAL_N)+127:0] tx_data;
input tx_clk;
output [127:0] tx_data;
// dma interface
output dac_clk;
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
output dac_valid_2;
output dac_enable_2;
input [63:0] dac_ddata_2;
output dac_valid_3;
output dac_enable_3;
input [63:0] dac_ddata_3;
input dac_dovf;
input dac_dunf;
output dac_clk;
output dac_valid_0;
output dac_enable_0;
input [ 63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [ 63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire up_clk;
wire up_rstn;
wire dac_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [255:0] tx_data_s;
wire [ 15:0] dac_data_0_0_s;
wire [ 15:0] dac_data_0_1_s;
wire [ 15:0] dac_data_0_2_s;
wire [ 15:0] dac_data_0_3_s;
wire [ 15:0] dac_data_1_0_s;
wire [ 15:0] dac_data_1_1_s;
wire [ 15:0] dac_data_1_2_s;
wire [ 15:0] dac_data_1_3_s;
wire [ 15:0] dac_data_2_0_s;
wire [ 15:0] dac_data_2_1_s;
wire [ 15:0] dac_data_2_2_s;
wire [ 15:0] dac_data_2_3_s;
wire [ 15:0] dac_data_3_0_s;
wire [ 15:0] dac_data_3_1_s;
wire [ 15:0] dac_data_3_2_s;
wire [ 15:0] dac_data_3_3_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
wire [ 15:0] dac_data_0_0_s;
wire [ 15:0] dac_data_0_1_s;
wire [ 15:0] dac_data_0_2_s;
wire [ 15:0] dac_data_0_3_s;
wire [ 15:0] dac_data_1_0_s;
wire [ 15:0] dac_data_1_1_s;
wire [ 15:0] dac_data_1_2_s;
wire [ 15:0] dac_data_1_3_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// dual/quad cores
assign tx_data = (PCORE_QUAD_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0];
// device interface
axi_ad9144_if i_if (
axi_ad9152_if i_if (
.tx_clk (tx_clk),
.tx_data (tx_data_s),
.tx_data (tx_data),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),
@ -197,19 +171,11 @@ module axi_ad9144 (
.dac_data_1_0 (dac_data_1_0_s),
.dac_data_1_1 (dac_data_1_1_s),
.dac_data_1_2 (dac_data_1_2_s),
.dac_data_1_3 (dac_data_1_3_s),
.dac_data_2_0 (dac_data_2_0_s),
.dac_data_2_1 (dac_data_2_1_s),
.dac_data_2_2 (dac_data_2_2_s),
.dac_data_2_3 (dac_data_2_3_s),
.dac_data_3_0 (dac_data_3_0_s),
.dac_data_3_1 (dac_data_3_1_s),
.dac_data_3_2 (dac_data_3_2_s),
.dac_data_3_3 (dac_data_3_3_s));
.dac_data_1_3 (dac_data_1_3_s));
// core
axi_ad9144_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
axi_ad9152_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),
@ -220,26 +186,12 @@ module axi_ad9144 (
.dac_data_1_1 (dac_data_1_1_s),
.dac_data_1_2 (dac_data_1_2_s),
.dac_data_1_3 (dac_data_1_3_s),
.dac_data_2_0 (dac_data_2_0_s),
.dac_data_2_1 (dac_data_2_1_s),
.dac_data_2_2 (dac_data_2_2_s),
.dac_data_2_3 (dac_data_2_3_s),
.dac_data_3_0 (dac_data_3_0_s),
.dac_data_3_1 (dac_data_3_1_s),
.dac_data_3_2 (dac_data_3_2_s),
.dac_data_3_3 (dac_data_3_3_s),
.dac_valid_0 (dac_valid_0),
.dac_enable_0 (dac_enable_0),
.dac_ddata_0 (dac_ddata_0),
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_valid_2 (dac_valid_2),
.dac_enable_2 (dac_enable_2),
.dac_ddata_2 (dac_ddata_2),
.dac_valid_3 (dac_valid_3),
.dac_enable_3 (dac_enable_3),
.dac_ddata_3 (dac_ddata_3),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),

2
library/axi_ad9152/axi_ad9152_channel.v
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@ -39,7 +39,7 @@
`timescale 1ns/100ps
module axi_ad9144_channel (
module axi_ad9152_channel (
// dac interface

88
library/axi_ad9152/axi_ad9152_core.v
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@ -39,7 +39,7 @@
`timescale 1ns/100ps
module axi_ad9144_core (
module axi_ad9152_core (
// dac interface
@ -53,14 +53,6 @@ module axi_ad9144_core (
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac_data_2_3,
dac_data_3_0,
dac_data_3_1,
dac_data_3_2,
dac_data_3_3,
// dma interface
@ -70,12 +62,6 @@ module axi_ad9144_core (
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_valid_2,
dac_enable_2,
dac_ddata_2,
dac_valid_3,
dac_enable_3,
dac_ddata_3,
dac_dovf,
dac_dunf,
@ -109,14 +95,6 @@ module axi_ad9144_core (
output [15:0] dac_data_1_1;
output [15:0] dac_data_1_2;
output [15:0] dac_data_1_3;
output [15:0] dac_data_2_0;
output [15:0] dac_data_2_1;
output [15:0] dac_data_2_2;
output [15:0] dac_data_2_3;
output [15:0] dac_data_3_0;
output [15:0] dac_data_3_1;
output [15:0] dac_data_3_2;
output [15:0] dac_data_3_3;
// dma interface
@ -126,12 +104,6 @@ module axi_ad9144_core (
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
output dac_valid_2;
output dac_enable_2;
input [63:0] dac_ddata_2;
output dac_valid_3;
output dac_enable_3;
input [63:0] dac_ddata_3;
input dac_dovf;
input dac_dunf;
@ -164,12 +136,6 @@ module axi_ad9144_core (
wire [31:0] up_rdata_1_s;
wire up_rack_1_s;
wire up_wack_1_s;
wire [31:0] up_rdata_2_s;
wire up_rack_2_s;
wire up_wack_2_s;
wire [31:0] up_rdata_3_s;
wire up_rack_3_s;
wire up_wack_3_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
@ -189,15 +155,15 @@ module axi_ad9144_core (
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s;
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s;
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s;
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s;
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s;
end
end
// dac channel
axi_ad9144_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 (
axi_ad9152_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0),
@ -218,7 +184,7 @@ module axi_ad9144_core (
// dac channel
axi_ad9144_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 (
axi_ad9152_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1),
@ -237,48 +203,6 @@ module axi_ad9144_core (
.up_rdata (up_rdata_1_s),
.up_rack (up_rack_1_s));
// dac channel
axi_ad9144_channel #(.CHID(2), .DP_DISABLE(DP_DISABLE)) i_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_2),
.dac_data ({dac_data_2_3, dac_data_2_2, dac_data_2_1, dac_data_2_0}),
.dma_data (dac_ddata_2),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_2_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_2_s),
.up_rack (up_rack_2_s));
// dac channel
axi_ad9144_channel #(.CHID(3), .DP_DISABLE(DP_DISABLE)) i_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_3),
.dac_data ({dac_data_3_3, dac_data_3_2, dac_data_3_1, dac_data_3_0}),
.dma_data (dac_ddata_3),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_3_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_3_s),
.up_rack (up_rack_3_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (

42
library/axi_ad9152/axi_ad9152_if.v
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@ -41,7 +41,7 @@
`timescale 1ns/100ps
module axi_ad9144_if (
module axi_ad9152_if (
// jesd interface
// tx_clk is (line-rate/40)
@ -60,21 +60,13 @@ module axi_ad9144_if (
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac_data_2_3,
dac_data_3_0,
dac_data_3_1,
dac_data_3_2,
dac_data_3_3);
dac_data_1_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [255:0] tx_data;
output [127:0] tx_data;
// dac interface
@ -88,18 +80,10 @@ module axi_ad9144_if (
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
input [15:0] dac_data_2_0;
input [15:0] dac_data_2_1;
input [15:0] dac_data_2_2;
input [15:0] dac_data_2_3;
input [15:0] dac_data_3_0;
input [15:0] dac_data_3_1;
input [15:0] dac_data_3_2;
input [15:0] dac_data_3_3;
// internal registers
reg [255:0] tx_data = 'd0;
reg [127:0] tx_data = 'd0;
// reorder data for the jesd links
@ -107,24 +91,8 @@ module axi_ad9144_if (
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 256'd0;
tx_data <= 128'd0;
end else begin
tx_data[255:248] <= dac_data_3_3[ 7: 0];
tx_data[247:240] <= dac_data_3_2[ 7: 0];
tx_data[239:232] <= dac_data_3_1[ 7: 0];
tx_data[231:224] <= dac_data_3_0[ 7: 0];
tx_data[223:216] <= dac_data_3_3[15: 8];
tx_data[215:208] <= dac_data_3_2[15: 8];
tx_data[207:200] <= dac_data_3_1[15: 8];
tx_data[199:192] <= dac_data_3_0[15: 8];
tx_data[191:184] <= dac_data_2_3[ 7: 0];
tx_data[183:176] <= dac_data_2_2[ 7: 0];
tx_data[175:168] <= dac_data_2_1[ 7: 0];
tx_data[167:160] <= dac_data_2_0[ 7: 0];
tx_data[159:152] <= dac_data_2_3[15: 8];
tx_data[151:144] <= dac_data_2_2[15: 8];
tx_data[143:136] <= dac_data_2_1[15: 8];
tx_data[135:128] <= dac_data_2_0[15: 8];
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];

18
library/axi_ad9152/axi_ad9152_ip.tcl
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@ -3,8 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9144
adi_ip_files axi_ad9144 [list \
adi_ip_create axi_ad9152
adi_ip_files axi_ad9152 [list \
"$ad_hdl_dir/library/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
@ -17,14 +17,14 @@ adi_ip_files axi_ad9144 [list \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"axi_ad9144_channel.v" \
"axi_ad9144_core.v" \
"axi_ad9144_if.v" \
"axi_ad9144.v" ]
"axi_ad9152_channel.v" \
"axi_ad9152_core.v" \
"axi_ad9152_if.v" \
"axi_ad9152.v" ]
adi_ip_properties axi_ad9144
adi_ip_constraints axi_ad9144 [list \
"axi_ad9144_constr.xdc" ]
adi_ip_properties axi_ad9152
adi_ip_constraints axi_ad9152 [list \
"axi_ad9152_constr.xdc" ]
ipx::save_core [ipx::current_core]

3
projects/ad9625_fmc/zc706/system_bd.tcl
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@ -37,7 +37,8 @@ connect_bd_net -net axi_ad9625_adc_valid [get_bd_pins axi_ad9625_core/adc_val
connect_bd_net -net axi_ad9625_adc_data [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon

390
projects/daq3/common/daq3_bd.tcl
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@ -1,8 +1,19 @@
# daq2
# daq3
if {$sys_zynq == 1} {
set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o]
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
} else {
set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o]
set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i]
}
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
@ -38,12 +49,6 @@ if {$sys_zynq == 0} {
set dac_valid_1 [create_bd_port -dir O dac_valid_1]
set dac_enable_1 [create_bd_port -dir O dac_enable_1]
set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1]
set dac_valid_2 [create_bd_port -dir O dac_valid_2]
set dac_enable_2 [create_bd_port -dir O dac_enable_2]
set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2]
set dac_valid_3 [create_bd_port -dir O dac_valid_3]
set dac_enable_3 [create_bd_port -dir O dac_enable_3]
set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3]
set dac_drd [create_bd_port -dir I dac_drd]
set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata]
@ -60,37 +65,36 @@ if {$sys_zynq == 0} {
# dac peripherals
set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core
set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9144_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9152_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma
set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9152_dma
set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
if {$sys_zynq == 1} {
set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect
set axi_ad9152_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9152_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9152_dma_interconnect
}
# adc peripherals
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9680_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
@ -116,29 +120,29 @@ if {$sys_zynq == 1} {
# dac/adc common gt/gpio
set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt
set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq3_gt
if {$sys_zynq == 1} {
set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect
set axi_daq3_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq3_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq3_gt_interconnect
}
# gpio and spi
if {$sys_zynq == 0} {
set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_daq2_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi
set axi_daq3_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_daq3_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq3_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq3_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq3_spi
set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio]
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio
set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio
set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio
set axi_daq3_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq3_gpio]
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq3_gpio
set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq3_gpio
set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq3_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq3_gpio
}
# additions to default configuration
@ -179,41 +183,35 @@ if {$sys_zynq == 1} {
if {$sys_zynq == 0} {
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq3_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq3_spi/ss_o]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq3_spi/sck_i]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq3_spi/sck_o]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq3_spi/io0_i]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq3_spi/io0_o]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq3_spi/io1_i]
} else {
set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat]
set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat
set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc
connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout]
connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
connect_bd_net -net spi_csn_2_o [get_bd_ports spi_csn_2_o] [get_bd_pins sys_ps7/SPI0_SS2_O]
connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
}
if {$sys_zynq == 0} {
connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i]
connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o]
connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t]
connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i]
connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o]
connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t]
connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq3_gpio/gpio_io_i]
connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq3_gpio/gpio_io_o]
connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq3_gpio/gpio_io_t]
connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq3_gpio/gpio2_io_i]
connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq3_gpio/gpio2_io_o]
connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq3_gpio/gpio2_io_t]
}
if {$sys_zynq == 0} {
@ -224,70 +222,64 @@ if {$sys_zynq == 0} {
# connections (gt)
connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk]
connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref]
connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p]
connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n]
connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync]
connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref]
connect_bd_net -net axi_daq3_gt_ref_clk_q [get_bd_pins axi_daq3_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_daq3_gt_ref_clk_c [get_bd_pins axi_daq3_gt/ref_clk_c] [get_bd_ports tx_ref_clk]
connect_bd_net -net axi_daq3_gt_rx_data_p [get_bd_pins axi_daq3_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_daq3_gt_rx_data_n [get_bd_pins axi_daq3_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_daq3_gt_rx_sync [get_bd_pins axi_daq3_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_daq3_gt_rx_ext_sysref [get_bd_pins axi_daq3_gt/rx_ext_sysref] [get_bd_ports rx_sysref]
connect_bd_net -net axi_daq3_gt_tx_data_p [get_bd_pins axi_daq3_gt/tx_data_p] [get_bd_ports tx_data_p]
connect_bd_net -net axi_daq3_gt_tx_data_n [get_bd_pins axi_daq3_gt/tx_data_n] [get_bd_ports tx_data_n]
connect_bd_net -net axi_daq3_gt_tx_sync [get_bd_pins axi_daq3_gt/tx_sync] [get_bd_ports tx_sync]
connect_bd_net -net axi_daq3_gt_tx_ext_sysref [get_bd_pins axi_daq3_gt/tx_ext_sysref] [get_bd_ports tx_sysref]
# connections (dac)
connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g]
connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk]
connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk]
connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk]
connect_bd_net -net axi_daq3_gt_tx_clk [get_bd_pins axi_daq3_gt/tx_clk_g]
connect_bd_net -net axi_daq3_gt_tx_clk [get_bd_pins axi_daq3_gt/tx_clk]
connect_bd_net -net axi_daq3_gt_tx_clk [get_bd_pins axi_ad9152_core/tx_clk]
connect_bd_net -net axi_daq3_gt_tx_clk [get_bd_pins axi_ad9152_jesd/tx_core_clk]
connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset]
connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref]
connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out]
connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out]
connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done]
connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync]
connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame]
connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata]
connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data]
connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk]
connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0]
connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0]
connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0]
connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1]
connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1]
connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1]
connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2]
connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2]
connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2]
connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3]
connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3]
connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3]
connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en]
connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_daq3_gt_tx_rst [get_bd_pins axi_daq3_gt/tx_rst] [get_bd_pins axi_ad9152_jesd/tx_reset]
connect_bd_net -net axi_daq3_gt_tx_sysref [get_bd_pins axi_daq3_gt/tx_sysref] [get_bd_pins axi_ad9152_jesd/tx_sysref]
connect_bd_net -net axi_daq3_gt_tx_gt_charisk [get_bd_pins axi_daq3_gt/tx_gt_charisk] [get_bd_pins axi_ad9152_jesd/gt_txcharisk_out]
connect_bd_net -net axi_daq3_gt_tx_gt_data [get_bd_pins axi_daq3_gt/tx_gt_data] [get_bd_pins axi_ad9152_jesd/gt_txdata_out]
connect_bd_net -net axi_daq3_gt_tx_rst_done [get_bd_pins axi_daq3_gt/tx_rst_done] [get_bd_pins axi_ad9152_jesd/tx_reset_done]
connect_bd_net -net axi_daq3_gt_tx_ip_sync [get_bd_pins axi_daq3_gt/tx_ip_sync] [get_bd_pins axi_ad9152_jesd/tx_sync]
connect_bd_net -net axi_daq3_gt_tx_ip_sof [get_bd_pins axi_daq3_gt/tx_ip_sof] [get_bd_pins axi_ad9152_jesd/tx_start_of_frame]
connect_bd_net -net axi_daq3_gt_tx_ip_data [get_bd_pins axi_daq3_gt/tx_ip_data] [get_bd_pins axi_ad9152_jesd/tx_tdata]
connect_bd_net -net axi_daq3_gt_tx_data [get_bd_pins axi_daq3_gt/tx_data] [get_bd_pins axi_ad9152_core/tx_data]
connect_bd_net -net axi_ad9152_dac_clk [get_bd_pins axi_ad9152_core/dac_clk] [get_bd_pins axi_ad9152_dma/fifo_rd_clk]
connect_bd_net -net axi_ad9152_dac_valid_0 [get_bd_pins axi_ad9152_core/dac_valid_0] [get_bd_ports dac_valid_0]
connect_bd_net -net axi_ad9152_dac_enable_0 [get_bd_pins axi_ad9152_core/dac_enable_0] [get_bd_ports dac_enable_0]
connect_bd_net -net axi_ad9152_dac_ddata_0 [get_bd_pins axi_ad9152_core/dac_ddata_0] [get_bd_ports dac_ddata_0]
connect_bd_net -net axi_ad9152_dac_valid_1 [get_bd_pins axi_ad9152_core/dac_valid_1] [get_bd_ports dac_valid_1]
connect_bd_net -net axi_ad9152_dac_enable_1 [get_bd_pins axi_ad9152_core/dac_enable_1] [get_bd_ports dac_enable_1]
connect_bd_net -net axi_ad9152_dac_ddata_1 [get_bd_pins axi_ad9152_core/dac_ddata_1] [get_bd_ports dac_ddata_1]
connect_bd_net -net axi_ad9152_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9152_dma/fifo_rd_en]
connect_bd_net -net axi_ad9152_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9152_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9152_dac_dunf [get_bd_pins axi_ad9152_core/dac_dunf] [get_bd_pins axi_ad9152_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In3]
# connections (adc)
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g]
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk]
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk]
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk]
connect_bd_net -net axi_daq3_gt_rx_clk [get_bd_pins axi_daq3_gt/rx_clk_g]
connect_bd_net -net axi_daq3_gt_rx_clk [get_bd_pins axi_daq3_gt/rx_clk]
connect_bd_net -net axi_daq3_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk]
connect_bd_net -net axi_daq3_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk]
connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset]
connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref]
connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in]
connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done]
connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out]
connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync]
connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame]
connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata]
connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data]
connect_bd_net -net axi_daq3_gt_rx_rst [get_bd_pins axi_daq3_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset]
connect_bd_net -net axi_daq3_gt_rx_sysref [get_bd_pins axi_daq3_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref]
connect_bd_net -net axi_daq3_gt_rx_gt_charisk [get_bd_pins axi_daq3_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_daq3_gt_rx_gt_disperr [get_bd_pins axi_daq3_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_daq3_gt_rx_gt_notintable [get_bd_pins axi_daq3_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_daq3_gt_rx_gt_data [get_bd_pins axi_daq3_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in]
connect_bd_net -net axi_daq3_gt_rx_rst_done [get_bd_pins axi_daq3_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done]
connect_bd_net -net axi_daq3_gt_rx_ip_comma_align [get_bd_pins axi_daq3_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out]
connect_bd_net -net axi_daq3_gt_rx_ip_sync [get_bd_pins axi_daq3_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync]
connect_bd_net -net axi_daq3_gt_rx_ip_sof [get_bd_pins axi_daq3_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame]
connect_bd_net -net axi_daq3_gt_rx_ip_data [get_bd_pins axi_daq3_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata]
connect_bd_net -net axi_daq3_gt_rx_data [get_bd_pins axi_daq3_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data]
connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0]
connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0]
@ -303,18 +295,18 @@ if {$sys_zynq == 0} {
# dac/adc clocks
connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk]
connect_bd_net -net axi_ad9152_dac_clk [get_bd_ports dac_clk]
connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9152_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9152_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9152_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq3_gt/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
@ -322,10 +314,10 @@ if {$sys_zynq == 0} {
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk]
@ -336,57 +328,57 @@ if {$sys_zynq == 0} {
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq3_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq3_gpio/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_spi/ext_spi_clk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gpio/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gpio/s_axi_aresetn]
connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
connect_bd_net -net axi_daq3_spi_irq [get_bd_pins axi_daq3_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_daq3_gpio_irq [get_bd_pins axi_daq3_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
}
# gt uses hp3, and 100MHz clock for both DRP and AXI4
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq3_gt/m_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gt/m_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_intf_net -intf_net axi_daq3_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq3_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_intf_net -intf_net axi_daq3_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq3_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq3_gt/m_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq3_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gt/m_axi_aresetn]
}
# memory interconnects share the same clock (fclk2)
@ -410,11 +402,11 @@ if {$sys_zynq == 1} {
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9152_dma/m_src_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn]
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source
@ -424,17 +416,17 @@ if {$sys_zynq == 0} {
} else {
connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_intf_net -intf_net axi_ad9152_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9152_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_intf_net -intf_net axi_ad9152_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9152_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9152_dma/m_src_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn]
connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
@ -451,58 +443,60 @@ if {$sys_zynq == 0} {
# ila
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon
connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data]
connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger]
connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
connect_bd_net -net axi_daq3_gt_rx_mon_data [get_bd_pins axi_daq3_gt/rx_mon_data]
connect_bd_net -net axi_daq3_gt_rx_mon_trigger [get_bd_pins axi_daq3_gt/rx_mon_trigger]
connect_bd_net -net axi_daq3_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_daq3_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_daq3_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
connect_bd_net -net axi_daq3_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_tx_mon]
set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon
connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data]
connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger]
connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK]
connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0]
connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1]
connect_bd_net -net axi_daq3_gt_tx_mon_data [get_bd_pins axi_daq3_gt/tx_mon_data]
connect_bd_net -net axi_daq3_gt_tx_mon_trigger [get_bd_pins axi_daq3_gt/tx_mon_trigger]
connect_bd_net -net axi_daq3_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK]
connect_bd_net -net axi_daq3_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0]
connect_bd_net -net axi_daq3_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9152_core/s_axi/axi_lite] SEG_data_ad9152_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq3_gt/s_axi/axi_lite] SEG_data_daq3_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9152_jesd/s_axi/Reg] SEG_data_ad9152_jesd
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9152_dma/s_axi/axi_lite] SEG_data_ad9152_dma
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq3_gpio/S_AXI/Reg] SEG_data_daq3_gpio
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq3_spi/axi_lite/Reg] SEG_data_daq3_spi
}
if {$sys_zynq == 0} {
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9152_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9152_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
}

7
projects/daq3/common/daq3_spi.v
View File

@ -37,14 +37,15 @@
`timescale 1ns/100ps
module daq2_spi (
module daq3_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
spi_sdio,
spi_dir);
// 4 wire
@ -56,6 +57,7 @@ module daq2_spi (
// 3 wire
inout spi_sdio;
output spi_dir;
// internal registers
@ -71,6 +73,7 @@ module daq2_spi (
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin

15
projects/daq3/zc706/system_bd.tcl
View File

@ -1,10 +1,10 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
source ../common/daq2_bd.tcl
source ../common/daq3_bd.tcl
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
@ -22,7 +22,7 @@ delete_bd_objs [get_bd_nets axi_ad9680_adc_ddata]
delete_bd_objs [get_bd_nets axi_ad9680_adc_dsync]
delete_bd_objs [get_bd_nets axi_ad9680_adc_dovf]
connect_bd_net -net [get_bd_nets axi_daq2_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst]
connect_bd_net -net [get_bd_nets axi_daq3_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq3_gt/rx_rst]
connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn]
connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req]
@ -40,18 +40,17 @@ connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync]
connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk]
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon
connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins ila_dma_mon/clk]
connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins ila_dma_mon/probe0]
connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins ila_dma_mon/probe1]
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins ila_dma_mon/probe2]
connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status]
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr

108
projects/daq3/zc706/system_constr.xdc
View File

@ -1,74 +1,62 @@
# daq3
# daq2
set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports sysref_p] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports sysref_n] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
# clocks
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk]
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk]
create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0]
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq3_gt_tx_clk]
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq3_gt_rx_clk]
set_clock_groups -asynchronous -group {tx_div_clk}
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {pl_ddr_clk}
set_clock_groups -asynchronous -group {pl_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

8
projects/daq3/zc706/system_project.tcl
View File

@ -4,14 +4,14 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create daq2_zc706
adi_project_files daq2_zc706 [list \
"../common/daq2_spi.v" \
adi_project_create daq3_zc706
adi_project_files daq3_zc706 [list \
"../common/daq3_spi.v" \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run daq2_zc706
adi_project_run daq3_zc706

81
projects/daq3/zc706/system_top.v
View File

@ -114,6 +114,8 @@ module system_top (
tx_data_p,
tx_data_n,
trig_p,
trig_n,
adc_fdb,
adc_fda,
dac_irq,
@ -121,16 +123,15 @@ module system_top (
adc_pd,
dac_txen,
dac_reset,
clkd_pd,
clkd_sync,
clkd_reset,
sysref_p,
sysref_n,
spi_csn_clk,
spi_csn_dac,
spi_csn_adc,
spi_clk,
spi_sdio);
spi_sdio,
spi_dir);
input sys_clk_p;
input sys_clk_n;
@ -205,6 +206,8 @@ module system_top (
output [ 3:0] tx_data_p;
output [ 3:0] tx_data_n;
input trig_p;
input trig_n;
inout adc_fdb;
inout adc_fda;
inout dac_irq;
@ -212,24 +215,21 @@ module system_top (
inout adc_pd;
inout dac_txen;
inout dac_reset;
inout clkd_pd;
inout clkd_sync;
inout clkd_reset;
output sysref_p;
output sysref_n;
output spi_csn_clk;
output spi_csn_dac;
output spi_csn_adc;
output spi_clk;
inout spi_sdio;
output spi_dir;
// internal registers
reg dac_drd = 'd0;
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg [63:0] dac_ddata_2 = 'd0;
reg [63:0] dac_ddata_3 = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [127:0] adc_ddata = 'd0;
@ -239,6 +239,8 @@ module system_top (
wire [42:0] gpio_i;
wire [42:0] gpio_o;
wire [42:0] gpio_t;
wire sysref;
wire trig;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
@ -252,12 +254,8 @@ module system_top (
wire [127:0] dac_ddata;
wire dac_enable_0;
wire dac_enable_1;
wire dac_enable_2;
wire dac_enable_3;
wire dac_valid_0;
wire dac_valid_1;
wire dac_valid_2;
wire dac_valid_3;
wire adc_clk;
wire [63:0] adc_data_0;
wire [63:0] adc_data_1;
@ -280,8 +278,6 @@ module system_top (
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b10: begin
dac_drd <= dac_valid_1 & ~dac_drd;
@ -297,8 +293,6 @@ module system_top (
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b01: begin
dac_drd <= dac_valid_0 & ~dac_drd;
@ -314,15 +308,11 @@ module system_top (
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
default: begin
dac_drd <= 1'b0;
dac_ddata_0 <= 64'd0;
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
endcase
end
@ -415,23 +405,32 @@ module system_top (
.IB (tx_sync_n),
.O (tx_sync));
daq2_spi i_spi (
daq3_spi i_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
.spi_sdio (spi_sdio),
.spi_dir (spi_dir));
ad_iobuf #(.DATA_WIDTH(26)) i_iobuf (
.dt ({gpio_t[42:32], gpio_t[14:0]}),
.di ({gpio_o[42:32], gpio_o[14:0]}),
.do ({gpio_i[42:32], gpio_i[14:0]}),
.dio ({ adc_pd, // 42
dac_txen, // 41
dac_reset, // 40
clkd_pd, // 39
clkd_sync, // 38
clkd_reset, // 37
OBUFDS i_obufds_sysref (
.I (gpio_o[40]),
.O (sysref_p),
.OB (sysref_n));
IBUFDS i_ibufds_trig (
.I (trig_p),
.IB (trig_n),
.O (trig));
assign gpio_i[39] = trig;
ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
.dt ({gpio_t[38:32], gpio_t[14:0]}),
.di ({gpio_o[38:32], gpio_o[14:0]}),
.do ({gpio_i[38:32], gpio_i[14:0]}),
.dio ({ adc_pd, // 38
dac_txen, // 37
adc_fdb, // 36
adc_fda, // 35
dac_irq, // 34
@ -492,17 +491,11 @@ module system_top (
.dac_ddata (dac_ddata),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_ddata_2 (dac_ddata_2),
.dac_ddata_3 (dac_ddata_3),
.dac_drd (dac_drd),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_enable_2 (dac_enable_2),
.dac_enable_3 (dac_enable_3),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.dac_valid_2 (dac_valid_2),
.dac_valid_3 (dac_valid_3),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
@ -518,8 +511,10 @@ module system_top (
.spdif (spdif),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),
.spi_csn_o (spi_csn),
.spi_csn_i (1'b1),
.spi_csn_0_o (spi_csn[0]),
.spi_csn_1_o (spi_csn[1]),
.spi_csn_2_o (spi_csn[2]),
.spi_sdi_i (spi_miso),
.spi_sdo_i (spi_mosi),
.spi_sdo_o (spi_mosi),