From c2dd991736430cb0f4e3ddef242ef4f09aeccffc Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 10 May 2017 14:32:57 -0400 Subject: [PATCH] axi_fmcadc5- sign-extend and interleave (core is too late) --- library/axi_fmcadc5_sync/axi_fmcadc5_sync.v | 12 ++++--- .../axi_fmcadc5_sync_calcor.v | 31 ++++++++++++------- 2 files changed, 28 insertions(+), 15 deletions(-) diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v index 48c8bd43a..6a250b91b 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v @@ -54,10 +54,12 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( output rx_sync_0_n, output rx_sync_1_p, output rx_sync_1_n, + input rx_enable_0, input [255:0] rx_data_0, + input rx_enable_1, input [255:0] rx_data_1, - output [255:0] rx_cor_data_0, - output [255:0] rx_cor_data_1, + output rx_cor_enable, + output [511:0] rx_cor_data, // calibration signal @@ -638,10 +640,12 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( axi_fmcadc5_sync_calcor i_calcor ( .rx_clk (rx_clk), + .rx_enable_0 (rx_enable_0), .rx_data_0 (rx_data_0), + .rx_enable_1 (rx_enable_1), .rx_data_1 (rx_data_1), - .rx_cor_data_0 (rx_cor_data_0), - .rx_cor_data_1 (rx_cor_data_1), + .rx_cor_enable (rx_cor_enable), + .rx_cor_data (rx_cor_data), .rx_cal_enable (rx_cal_enable), .rx_cal_done_t (rx_cal_done_t_s), .rx_cal_max_0 (rx_cal_max_0_s), diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v index b0923b0de..60f0ae001 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v @@ -44,11 +44,13 @@ module axi_fmcadc5_sync_calcor ( // receive interface - input rx_clk, + input rx_clk, + input rx_enable_0, input [255:0] rx_data_0, + input rx_enable_1, input [255:0] rx_data_1, - output [255:0] rx_cor_data_0, - output [255:0] rx_cor_data_1, + output rx_cor_enable, + output [511:0] rx_cor_data, // calibration signals @@ -65,8 +67,9 @@ module axi_fmcadc5_sync_calcor ( // internal registers - reg [ 15:0] rx_cor_data_int_0[0:15]; - reg [ 15:0] rx_cor_data_int_1[0:15]; + reg rx_cor_enable_int = 'd0; + reg [ 15:0] rx_cor_data_0[0:15]; + reg [ 15:0] rx_cor_data_1[0:15]; reg rx_cal_done_int_t = 'd0; reg [ 15:0] rx_cal_max_0_6 = 'd0; reg [ 15:0] rx_cal_min_0_6 = 'd0; @@ -106,10 +109,16 @@ module axi_fmcadc5_sync_calcor ( // offset & gain + assign rx_cor_enable = rx_cor_enable_int; + + always @(posedge rx_clk) begin + rx_cor_enable_int = rx_enable_0 & rx_enable_1; + end + generate for (n = 0; n <= 15; n = n + 1) begin: g_rx_cal_data - assign rx_cor_data_0[((n*16)+15):(n*16)] = rx_cor_data_0_s[n][30:15]; - assign rx_cor_data_1[((n*16)+15):(n*16)] = rx_cor_data_1_s[n][30:15]; + assign rx_cor_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15]; + assign rx_cor_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15]; end endgenerate @@ -119,14 +128,14 @@ module axi_fmcadc5_sync_calcor ( for (n = 0; n <= 15; n = n + 1) begin: g_rx_gain ad_mul #(.DELAY_DATA_WIDTH(1)) i_rx_gain_0 ( .clk (rx_clk), - .data_a ({rx_cor_data_int_0[n][15], rx_cor_data_int_0[n]}), + .data_a ({rx_cor_data_0[n][15], rx_cor_data_0[n]}), .data_b ({1'b0, rx_cor_scale_0}), .data_p (rx_cor_data_0_s[n]), .ddata_in (1'd0), .ddata_out ()); ad_mul #(.DELAY_DATA_WIDTH(1)) i_rx_gain_1 ( .clk (rx_clk), - .data_a ({rx_cor_data_int_1[n][15], rx_cor_data_int_1[n]}), + .data_a ({rx_cor_data_1[n][15], rx_cor_data_1[n]}), .data_b ({1'b0, rx_cor_scale_1}), .data_p (rx_cor_data_1_s[n]), .ddata_in (1'd0), @@ -139,8 +148,8 @@ module axi_fmcadc5_sync_calcor ( generate for (n = 0; n <= 15; n = n + 1) begin: g_rx_offset always @(posedge rx_clk) begin - rx_cor_data_int_0[n] <= rx_data_0_s[n] + rx_cor_offset_0; - rx_cor_data_int_1[n] <= rx_data_1_s[n] + rx_cor_offset_1; + rx_cor_data_0[n] <= rx_data_0_s[n] + rx_cor_offset_0; + rx_cor_data_1[n] <= rx_data_1_s[n] + rx_cor_offset_1; end end endgenerate