axi_adrv9001: Add external sync support
The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.main
parent
38c489d254
commit
c2d960e029
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@ -51,12 +51,17 @@ module axi_adrv9001 #(
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter EXT_SYNC = 0,
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parameter USE_RX_CLK_FOR_TX = 0
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) (
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input ref_clk,
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input mssi_sync,
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input tx_output_enable,
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// external synchronization signals
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input adc_sync_in,
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input dac_sync_in,
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// physical interface
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input rx1_dclk_in_n_NC,
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input rx1_dclk_in_p_dclk_in,
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@ -416,7 +421,8 @@ module axi_adrv9001 #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE)
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.DEV_PACKAGE (DEV_PACKAGE),
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.EXT_SYNC (EXT_SYNC)
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) i_core (
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// ADC interface
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.rx1_clk (adc_1_clk),
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@ -530,6 +536,10 @@ module axi_adrv9001 #(
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.tdd_tx2_rf_en (tdd_tx2_rf_en),
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.tdd_if2_mode (tdd_if2_mode),
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.ref_clk (ref_clk),
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.adc_sync_in (adc_sync_in),
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.dac_sync_in (dac_sync_in),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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@ -13,3 +13,24 @@ set_false_path \
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set_false_path \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_tx1_ctrl_sync* && IS_SEQUENTIAL}]
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# sync event i_rx_external_sync
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/out_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}]
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/in_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
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# sync event i_tx_external_sync
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/out_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}]
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/in_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
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# mssi_sync
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set_false_path \
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-to [get_cells -quiet -hier *mssi_sync_d_reg* \
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-filter {NAME =~ *i_*_phy* && IS_SEQUENTIAL}]
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@ -51,6 +51,7 @@ module axi_ad9001_core #(
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter EXT_SYNC = 0,
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parameter DAC_DDS_TYPE = 1,
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parameter DAC_DDS_CORDIC_DW = 20,
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@ -169,6 +170,11 @@ module axi_ad9001_core #(
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output tdd_tx2_rf_en,
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output tdd_if2_mode,
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// external syncronization signals
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input adc_sync_in,
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input dac_sync_in,
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input ref_clk,
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// processor interface
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input up_rstn,
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@ -210,6 +216,10 @@ module axi_ad9001_core #(
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wire tx2_sdr_ddr_n_loc;
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wire tx2_symb_op_loc;
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wire tx2_symb_8_16b_loc;
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wire adc_sync;
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wire adc_sync_m;
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wire dac_sync_m;
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wire dac_sync_out_1;
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reg tx1_data_valid_A_d;
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reg [15:0] tx1_data_i_A_d;
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@ -220,6 +230,14 @@ module axi_ad9001_core #(
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reg tx2_data_valid_A_d;
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reg [15:0] tx2_data_i_A_d;
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reg [15:0] tx2_data_q_A_d;
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reg sync_adc_valid = 1'b1;
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reg adc_sync_armed = 1'b0;
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reg adc_sync_in_d1 = 1'b0;
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reg adc_sync_d1 = 1'b0;
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reg dac_sync_arm = 1'b0;
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reg dac_ext_sync_arm_d = 1'b0;
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reg dac_sync_in_d1 = 1'b0;
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reg external_dac_sync = 1'b0;
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// rx1_r1_mode and tx1_r1_mode considered static during operation
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// rx1_r1_mode should be 0 only when rx1_clk and rx2_clk have the same frequency
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@ -304,6 +322,59 @@ module axi_ad9001_core #(
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end
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end
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sync_event #(
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.NUM_OF_EVENTS (1),
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.ASYNC_CLK (1))
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i_rx_external_sync (
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.in_clk (ref_clk),
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.in_event (adc_sync_in),
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.out_clk (rx1_clk),
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.out_event (adc_sync_m));
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always @(posedge rx1_clk) begin
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if (rx1_rst == 1'b1) begin
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adc_sync_armed <= 1'b0;
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adc_sync_in_d1 <= 1'b0;
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adc_sync_d1 <= 1'b0;
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sync_adc_valid <= 1'b1;
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end else begin
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adc_sync_in_d1 <= adc_sync_m;
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adc_sync_d1 <= adc_sync;
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if (~adc_sync_d1 & adc_sync) begin
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sync_adc_valid <= 1'b0;
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adc_sync_armed <= 1'b1;
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end else if (~adc_sync_in_d1 & adc_sync_m & adc_sync_armed) begin
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sync_adc_valid <= 1'b1;
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adc_sync_armed <= 1'b0;
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end
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end
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end
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sync_event #(
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.NUM_OF_EVENTS (1),
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.ASYNC_CLK (1))
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i_tx_external_sync (
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.in_clk (ref_clk),
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.in_event (dac_sync_in),
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.out_clk (tx1_clk),
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.out_event (dac_sync_m));
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always @(posedge tx1_clk) begin
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if (tx1_rst == 1'b1) begin
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dac_ext_sync_arm_d <= 1'b0;
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dac_sync_in_d1 <= 1'b0;
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external_dac_sync <= 1'b0;
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end else begin
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dac_sync_in_d1 <= dac_sync_m;
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dac_ext_sync_arm_d <= dac_ext_sync_arm;
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if (~dac_ext_sync_arm_d & dac_ext_sync_arm) begin
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external_dac_sync <= ~external_dac_sync;
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end else if (~dac_sync_in_d1 & dac_sync_m) begin
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external_dac_sync <= 1'b0;
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end
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end
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end
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axi_adrv9001_rx #(
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.ID (ID),
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.ENABLED (1),
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@ -321,11 +392,11 @@ module axi_ad9001_core #(
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i_rx1 (
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.adc_rst (rx1_rst),
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.adc_clk (rx1_clk),
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.adc_valid_A (rx1_data_valid & tdd_rx1_valid),
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.adc_valid_A (rx1_data_valid & tdd_rx1_valid & sync_adc_valid),
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.adc_data_i_A (rx1_data_i),
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.adc_data_q_A (rx1_data_q),
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.adc_valid_B (rx2_data_valid & tdd_rx1_valid),
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.adc_valid_B (rx2_data_valid & tdd_rx1_valid & sync_adc_valid),
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.adc_data_i_B (rx2_data_i),
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.adc_data_q_B (rx2_data_q),
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@ -357,6 +428,7 @@ module axi_ad9001_core #(
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.adc_data_q1 (adc_1_data_q1[15:0]),
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.adc_dovf (adc_1_dovf),
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.adc_sync (adc_sync),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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@ -385,7 +457,7 @@ module axi_ad9001_core #(
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i_rx2 (
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.adc_rst (rx2_rst_loc),
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.adc_clk (rx2_clk),
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.adc_valid_A (rx2_data_valid & tdd_rx2_valid),
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.adc_valid_A (rx2_data_valid & tdd_rx2_valid & sync_adc_valid),
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.adc_data_i_A (rx2_data_i),
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.adc_data_q_A (rx2_data_q),
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@ -438,6 +510,7 @@ module axi_ad9001_core #(
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.EXT_SYNC (EXT_SYNC),
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.DDS_DISABLE (DDS_DISABLE),
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.IQCORRECTION_DISABLE (1),
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.DAC_DDS_TYPE (DAC_DDS_TYPE),
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@ -459,8 +532,9 @@ module axi_ad9001_core #(
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.up_dac_r1_mode (up_tx1_r1_mode),
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.tdd_tx_valid (tdd_tx1_valid),
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.dac_clk_ratio (dac_clk_ratio),
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.dac_sync_in (1'b0),
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.dac_sync_out (),
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.dac_sync_in (external_dac_sync | dac_sync_out_1),
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.dac_sync_out (dac_sync_out_1),
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.dac_ext_sync_arm (dac_ext_sync_arm),
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.dac_enable_i0 (dac_1_enable_i0),
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.dac_valid (dac_1_valid),
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.dac_data_i0 (dac_1_data_i0[15:0]),
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@ -494,6 +568,7 @@ module axi_ad9001_core #(
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.EXT_SYNC (EXT_SYNC),
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.DDS_DISABLE (DDS_DISABLE),
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.IQCORRECTION_DISABLE (1),
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.DAC_DDS_TYPE (DAC_DDS_TYPE),
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@ -512,7 +587,7 @@ module axi_ad9001_core #(
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.dac_sdr_ddr_n (tx2_sdr_ddr_n_loc),
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.dac_symb_op (tx2_symb_op_loc),
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.dac_symb_8_16b (tx2_symb_8_16b_loc),
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.dac_sync_in (1'b0),
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.dac_sync_in (external_dac_sync | dac_sync_out_1),
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.dac_sync_out (),
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.dac_valid (dac_2_valid),
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.dac_enable_i0 (dac_2_enable_i0),
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@ -62,35 +62,55 @@ adi_ip_add_core_dependencies { \
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analog.com:user:util_cdc:1.0 \
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}
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ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface adc_1_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface adc_2_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_1_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_2_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface adc_1_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface adc_2_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_1_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_2_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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set cc [ipx::current_core]
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_1_rst -of_objects [ipx::current_core]]
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_2_rst -of_objects [ipx::current_core]]
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_1_rst -of_objects [ipx::current_core]]
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_2_rst -of_objects [ipx::current_core]]
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ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 $cc
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ipx::infer_bus_interface adc_1_clk xilinx.com:signal:clock_rtl:1.0 $cc
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ipx::infer_bus_interface adc_2_clk xilinx.com:signal:clock_rtl:1.0 $cc
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ipx::infer_bus_interface dac_1_clk xilinx.com:signal:clock_rtl:1.0 $cc
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ipx::infer_bus_interface dac_2_clk xilinx.com:signal:clock_rtl:1.0 $cc
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ipx::infer_bus_interface adc_1_rst xilinx.com:signal:reset_rtl:1.0 $cc
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ipx::infer_bus_interface adc_2_rst xilinx.com:signal:reset_rtl:1.0 $cc
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ipx::infer_bus_interface dac_1_rst xilinx.com:signal:reset_rtl:1.0 $cc
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ipx::infer_bus_interface dac_2_rst xilinx.com:signal:reset_rtl:1.0 $cc
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_1_rst -of_objects $cc]
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_2_rst -of_objects $cc]
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_1_rst -of_objects $cc]
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ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_2_rst -of_objects $cc]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT')) == 1 && spirit:decode(id('MODELPARAM_VALUE.DISABLE_TX2_SSI')) == 0} \
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[ipx::get_ports dac_2* -of_objects [ipx::current_core]]
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[ipx::get_ports dac_2* -of_objects $cc]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT')) == 1 && spirit:decode(id('MODELPARAM_VALUE.DISABLE_RX2_SSI')) == 0} \
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[ipx::get_ports adc_2* -of_objects [ipx::current_core]]
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[ipx::get_ports adc_2* -of_objects $cc]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.DISABLE_TX2_SSI')) == 0} \
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[ipx::get_ports *tx2_* -of_objects [ipx::current_core]]
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[ipx::get_ports *tx2_* -of_objects $cc]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.DISABLE_RX2_SSI')) == 0} \
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[ipx::get_ports *rx2_* -of_objects [ipx::current_core]]
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[ipx::get_ports *rx2_* -of_objects $cc]
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set_property driver_value 0 [ipx::get_ports *_sync_in* -of_objects $cc]
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## Customize XGUI layout
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set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
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ipgui::add_param -name "EXT_SYNC" -component $cc -parent $page0
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set_property -dict [list \
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"display_name" "External sync" \
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"tooltip" "NOTE: If active enables the external synchronization features for Rx and Tx. The external sync signals must be synchronous with to ref_clk" \
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"widget" "checkBox" \
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] [ipgui::get_guiparamspec -name "EXT_SYNC" -component $cc]
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adi_set_ports_dependency "adc_sync_in" \
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"(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC')) == 1)"
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adi_set_ports_dependency "dac_sync_in" \
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"(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC')) == 1)"
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adi_add_auto_fpga_spec_params
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ipx::create_xgui_files [ipx::current_core]
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ipx::create_xgui_files $cc
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ipx::save_core [ipx::current_core]
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ipx::save_core $cc
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@ -93,6 +93,8 @@ module axi_adrv9001_rx #(
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input adc_dovf,
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output adc_sync,
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// processor interface
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input up_rstn,
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input up_clk,
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@ -362,7 +364,7 @@ end else begin : core_enabled
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.adc_clk_ratio (adc_clk_ratio),
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.adc_start_code (),
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.adc_sref_sync (),
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.adc_sync (),
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.adc_sync (adc_sync),
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.adc_num_lanes (adc_num_lanes),
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.adc_sdr_ddr_n (adc_sdr_ddr_n),
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.adc_symb_op (adc_symb_op),
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@ -47,6 +47,7 @@ module axi_adrv9001_tx #(
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter EXT_SYNC = 0,
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parameter DISABLE = 0,
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parameter DDS_DISABLE = 0,
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parameter IQCORRECTION_DISABLE = 0,
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@ -78,6 +79,7 @@ module axi_adrv9001_tx #(
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// master/slave
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input dac_sync_in,
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output dac_sync_out,
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output dac_ext_sync_arm,
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// dma interface
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output dac_valid,
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@ -166,7 +168,7 @@ end else begin : core_enabled
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// master/slave
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||||
assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
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||||
assign dac_data_sync_s = (EXT_SYNC == 0) ? dac_sync_out : dac_sync_in;
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always @(posedge dac_clk) begin
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dac_data_sync <= dac_data_sync_s;
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|
@ -377,6 +379,7 @@ end else begin : core_enabled
|
|||
.dac_symb_op (dac_symb_op),
|
||||
.dac_symb_8_16b (dac_symb_8_16b),
|
||||
.dac_sync (dac_sync_out),
|
||||
.dac_ext_sync_arm (dac_ext_sync_arm),
|
||||
.dac_frame (),
|
||||
.dac_clksel (),
|
||||
.dac_par_type (),
|
||||
|
|
Loading…
Reference in New Issue