pulsar_adc_pmdz: Initial commit
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StancaPop
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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# PULSAR_ADC_PMDZ HDL Project
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/eval-ad400x-fmcz)
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* Parts : [AD7942: 14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP](https://www.analog.com/ad7942)
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* Parts : [AD7946: 14-Bit, 500 kSPS PulSAR ADC in MSOP](https://www.analog.com/ad7946)
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* Parts : [AD7988-1: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-1)
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* Parts : [AD7685: 16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN](https://www.analog.com/ad7685)
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* Parts : [AD7687: 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7687)
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* Parts : [AD7691: 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7691)
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* Parts : [AD7686: 500 kSPS 16-BIT PulSAR A/D Converter in MSOP/QFN](https://www.analog.com/ad7686)
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* Parts : [AD7688: 500 kSPS 16- BIT Differential PulSAR A/D Converter in µSOIC/QFN](https://www.analog.com/ad7688)
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* Parts : [AD7693: 16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential A/D Converter in MSOP/QFN](https://www.analog.com/ad7693)
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* Parts : [AD7988-5: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-5)
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* Parts : [AD7980: 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7980)
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* Parts : [AD7983: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7983)
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* Parts : [AD7690: 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7690)
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* Project Doc: https://wiki.analog.com/resources/eval/10-lead-pulsar-adc-evaluation-board
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/pulsar_adc_pmods_hdl
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7476a
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## Supported parts
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* AD7942
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* AD7946
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* AD7988-1
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* AD7685
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* AD7687
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* AD7691
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* AD7686
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* AD7688
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* AD7693
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* AD7988-5
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* AD7980
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* AD7983
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* AD7690
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* AD7982
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* AD7984
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 pulsar_adc_spi
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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set data_width 32
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set async_spi_clk 1
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set num_cs 1
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set num_sdi 1
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set sdi_delay 1
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set hier_spi_engine spi_pulsar_adc
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
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ad_ip_instance axi_pwm_gen pulsar_adc_trigger_gen
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ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_PERIOD 120
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ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_WIDTH 1
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_pulsar_adc_dma
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
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ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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ad_connect spi_clk pulsar_adc_trigger_gen/ext_clk
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ad_connect $sys_cpu_clk pulsar_adc_trigger_gen/s_axi_aclk
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ad_connect sys_cpu_resetn pulsar_adc_trigger_gen/s_axi_aresetn
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ad_connect pulsar_adc_trigger_gen/pwm_0 $hier_spi_engine/offload/trigger
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ad_connect axi_pulsar_adc_dma/s_axis spi_pulsar_adc/M_AXIS_SAMPLE
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ad_connect spi_pulsar_adc/m_spi pulsar_adc_spi
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ad_connect $sys_cpu_clk spi_pulsar_adc/clk
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ad_connect spi_clk spi_pulsar_adc/spi_clk
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ad_connect spi_clk axi_pulsar_adc_dma/s_axis_aclk
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ad_connect sys_cpu_resetn spi_pulsar_adc/resetn
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ad_connect sys_cpu_resetn axi_pulsar_adc_dma/m_dest_axi_aresetn
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ad_cpu_interconnect 0x44a00000 spi_pulsar_adc/axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_pulsar_adc_dma
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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ad_cpu_interconnect 0x44b00000 pulsar_adc_trigger_gen
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ad_cpu_interrupt "ps-13" "mb-13" axi_pulsar_adc_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi_pulsar_adc/irq
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ad_mem_hp0_interconnect sys_cpu_clk axi_pulsar_adc_dma/m_dest_axi
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := pulsar_adc_pmdz_coraz7s
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M_DEPS += ../common/pulsar_adc_pmdz_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
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M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
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M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_sysid
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LIB_DEPS += spi_engine/axi_spi_engine
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LIB_DEPS += spi_engine/spi_engine_execution
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LIB_DEPS += spi_engine/spi_engine_interconnect
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LIB_DEPS += spi_engine/spi_engine_offload
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LIB_DEPS += sysid_rom
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include ../../scripts/project-xilinx.mk
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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source ../common/pulsar_adc_pmdz_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file
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# ad40xx_fmc SPI interface
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set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo] ; ## PMOD JA [2]
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set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdi] ; ## PMOD JA [1]
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set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sclk] ; ## PMOD JA [3]
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set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_cs] ; ## PMOD JA [0]
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set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports pulsar_adc_spi_pd] ; ## PMOD JA [4]
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# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
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# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
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create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
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# relax the SDO path to help closing timing at high frequencies
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set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
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set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
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set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
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set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project pulsar_adc_pmdz_coraz7s
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adi_project_files pulsar_adc_pmdz_coraz7s [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
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adi_project_run pulsar_adc_pmdz_coraz7s
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 - 2021 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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output pulsar_adc_spi_cs,
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output pulsar_adc_spi_sclk,
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input pulsar_adc_spi_sdi,
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output pulsar_adc_spi_sdo,
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output pulsar_adc_spi_pd,
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inout [ 1:0] btn,
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inout [ 5:0] led);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// instantiations
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assign gpio_i[31:8] = gpio_o[31:8];
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assign gpio_i[63:33] = gpio_o[63:33];
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_admp_pd_iobuf (
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.dio_t(gpio_t[32]),
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.dio_i(gpio_o[32]),
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.dio_o(gpio_i[32]),
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.dio_p(pulsar_adc_spi_pd));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iobuf_buttons (
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.dio_t(gpio_t[1:0]),
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.dio_i(gpio_o[1:0]),
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.dio_o(gpio_i[1:0]),
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.dio_p(btn));
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ad_iobuf #(
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.DATA_WIDTH(6)
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) i_iobuf_leds (
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.dio_t(gpio_t[7:2]),
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.dio_i(gpio_o[7:2]),
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.dio_o(gpio_i[7:2]),
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.dio_p(led));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
|
||||||
|
.ddr_dqs_p (ddr_dqs_p),
|
||||||
|
.ddr_odt (ddr_odt),
|
||||||
|
.ddr_ras_n (ddr_ras_n),
|
||||||
|
.ddr_reset_n (ddr_reset_n),
|
||||||
|
.ddr_we_n (ddr_we_n),
|
||||||
|
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||||
|
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||||
|
.fixed_io_mio (fixed_io_mio),
|
||||||
|
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||||
|
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||||
|
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||||
|
.gpio_i (gpio_i),
|
||||||
|
.gpio_o (gpio_o),
|
||||||
|
.gpio_t (gpio_t),
|
||||||
|
.spi0_clk_i (1'b0),
|
||||||
|
.spi0_clk_o (),
|
||||||
|
.spi0_csn_0_o (),
|
||||||
|
.spi0_csn_1_o (),
|
||||||
|
.spi0_csn_2_o (),
|
||||||
|
.spi0_csn_i (1'b1),
|
||||||
|
.spi0_sdi_i (1'b0),
|
||||||
|
.spi0_sdo_i (1'b0),
|
||||||
|
.spi0_sdo_o (),
|
||||||
|
.spi1_clk_i (1'b0),
|
||||||
|
.spi1_clk_o (),
|
||||||
|
.spi1_csn_0_o (),
|
||||||
|
.spi1_csn_1_o (),
|
||||||
|
.spi1_csn_2_o (),
|
||||||
|
.spi1_csn_i (1'b1),
|
||||||
|
.spi1_sdi_i (1'b0),
|
||||||
|
.spi1_sdo_i (1'b0),
|
||||||
|
.spi1_sdo_o (),
|
||||||
|
.pulsar_adc_spi_cs(pulsar_adc_spi_cs),
|
||||||
|
.pulsar_adc_spi_sclk(pulsar_adc_spi_sclk),
|
||||||
|
.pulsar_adc_spi_sdi(pulsar_adc_spi_sdi),
|
||||||
|
.pulsar_adc_spi_sdo(pulsar_adc_spi_sdo),
|
||||||
|
.pulsar_adc_spi_sdo_t(),
|
||||||
|
.pulsar_adc_spi_three_wire()
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue