scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect
Laszlo Nagy
Laszlo Nagy
parent
4d12c4d99a
commit
c22f622599
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@ -493,10 +493,12 @@ proc ad_mem_hp0_interconnect {p_clk p_name} {
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global sys_zynq
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if {($sys_zynq <= 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
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if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
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if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
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if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
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if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
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}
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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@ -509,10 +511,12 @@ proc ad_mem_hp1_interconnect {p_clk p_name} {
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global sys_zynq
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if {($sys_zynq <= 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
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if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
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if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
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if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
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if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
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}
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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@ -525,10 +529,12 @@ proc ad_mem_hp2_interconnect {p_clk p_name} {
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global sys_zynq
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if {($sys_zynq <= 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
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if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
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if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
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if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
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if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
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}
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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@ -541,10 +547,12 @@ proc ad_mem_hp3_interconnect {p_clk p_name} {
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global sys_zynq
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if {($sys_zynq <= 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
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if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
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if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
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if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
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if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
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}
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, proc is
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@ -676,6 +684,13 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_*]
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}
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if {$p_sel eq "NOC"} {
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set m_interconnect_index [get_property CONFIG.NUM_SI [get_bd_cells axi_noc_0]]
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set m_interconnect_cell [get_bd_cells axi_noc_0]
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set m_addr_seg [get_bd_addr_segs axi_noc_0/S[format "%02s" [expr $m_interconnect_index +1]]_AXI/C0_DDR_LOW0]
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set sys_mem_clk_index [expr [get_property CONFIG.NUM_CLKS [get_bd_cells axi_noc_0]]-1]
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}
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set i_str "S$m_interconnect_index"
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if {$m_interconnect_index < 10} {
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set i_str "S0$m_interconnect_index"
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@ -710,16 +725,30 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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} else {
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set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
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if {[lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]] == -1 } {
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set clk_index [lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]]
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if { $clk_index == -1 } {
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incr sys_mem_clk_index
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set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
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ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
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set asocc_clk_pin $m_interconnect_cell/ACLK$sys_mem_clk_index
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} else {
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set asocc_clk_pin [lindex [get_bd_pins $m_interconnect_cell/ACLK*] $clk_index]
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}
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ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
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if {$p_intf_clock ne ""} {
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ad_connect $p_clk $p_intf_clock
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}
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if {$p_sel eq "NOC"} {
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set_property -dict [list CONFIG.CONNECTIONS {MC_0 { read_bw {1720} write_bw {1720} read_avg_burst {4} write_avg_burst {4}} }] [get_bd_intf_pins /axi_noc_0/${i_str}_AXI]
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# Add the new bus as associated to the clock pin, append new if other exists
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set clk_asoc_port [get_property CONFIG.ASSOCIATED_BUSIF [get_bd_pins $asocc_clk_pin]]
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if {$clk_asoc_port != {}} {
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set clk_asoc_port ${clk_asoc_port}:
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}
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set_property -dict [list CONFIG.ASSOCIATED_BUSIF ${clk_asoc_port}${i_str}_AXI] [get_bd_pins $asocc_clk_pin]
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}
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set mem_mapped ""
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if {$p_sel eq "MEM"} {
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set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of [get_bd_intf_pins -filter {NAME=~ *DLMB*} -of [get_bd_cells /sys_mb]]] -filter {NAME=~ *DDR* || NAME=~ *ddr*}]
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@ -768,6 +797,10 @@ proc ad_cpu_interconnect {p_address p_name} {
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]
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ad_connect sys_cpu_clk axi_cpu_interconnect/aclk
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ad_connect sys_cpu_resetn axi_cpu_interconnect/aresetn
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if {$sys_zynq == 3} {
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ad_connect sys_cpu_clk sys_cips/m_axi_fpd_aclk
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ad_connect axi_cpu_interconnect/S00_AXI sys_cips/M_AXI_FPD
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}
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if {$sys_zynq == 2} {
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ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
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ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
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@ -784,6 +817,9 @@ proc ad_cpu_interconnect {p_address p_name} {
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}
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}
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if {$sys_zynq == 3} {
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set sys_addr_cntrl_space [get_bd_addr_spaces /sys_cips/M_AXI_FPD]
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}
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if {$sys_zynq == 2} {
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set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
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}
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@ -897,6 +933,18 @@ proc ad_cpu_interconnect {p_address p_name} {
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if {$p_seg_range < 0x1000} {
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set p_seg_range 0x1000
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}
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if {$sys_zynq == 3} {
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if {($p_address >= 0x44000000) && ($p_address <= 0x4fffffff)} {
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# place axi peripherics in A400_0000-AFFF_FFFF range
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set p_address [expr ($p_address + 0x60000000)]
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} elseif {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
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# place axi peripherics in B000_0000-BFFF_FFFF range
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set p_address [expr ($p_address + 0x40000000)]
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} else {
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error "ERROR: ad_cpu_interconnect : Cannot map ($p_address) to aperture, \
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Addess out of range 0x4400_0000 - 0X4FFF_FFFF; 0x7000_0000 - 0X7FFF_FFFF !"
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}
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}
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if {$sys_zynq == 2} {
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if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
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set p_address [expr ($p_address + 0x40000000)]
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@ -931,6 +979,13 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
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set p_index [regsub -all {[^0-9]} $p_index_int ""]
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set m_index [expr ($p_index - 8)]
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if {$sys_zynq == 3} {
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if {$p_index < 0 || $p_index > 15} {
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error "ERROR: ad_cpu_interrupt : Interrupt index ($p_index) out of range 0-15 "
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}
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ad_connect $p_name sys_cips/pl_ps_irq$p_index
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}
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if {($sys_zynq == 2) && ($p_index <= 7)} {
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set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
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set p_pin [get_bd_pins sys_concat_intc_0/In$p_index]
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