arradio c5soc: Update project to tcl flow.

-Update to tcl flow
 -Add missing i2c interface

projects/arradio/c5soc/Makefile

@@ -34,6 +34,7 @@ M_FLIST += *.sta.*
 M_FLIST += *.qsf
 M_FLIST += *.qpf
 M_FLIST += *.qws
+M_FLIST += *.qsys
 M_FLIST += *.sof
 M_FLIST += *.cdf
 M_FLIST += *.sld
@@ -50,6 +51,7 @@ M_FLIST +=  *.jdi
 M_FLIST += *.pin
 M_FLIST += *_summary.csv
 M_FLIST += *.dpf
+M_FLIST += system_qsys_script.tcl
 
 
 

projects/arradio/c5soc/system_project.tcl

@@ -91,6 +91,18 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
 
+set_location_assignment PIN_F15 -to scl
+set_location_assignment PIN_G13 -to sda
+set_location_assignment PIN_C7  -to ga0
+set_location_assignment PIN_H14 -to ga1
+set_instance_assignment -name IO_STANDARD "2.5 V" -to scl
+set_instance_assignment -name IO_STANDARD "2.5 V" -to sda
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ga0
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ga1
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to scl
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sda
+
 set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity axi_ad9361
 
 execute_flow -compile

projects/arradio/c5soc/system_top.v

@@ -100,6 +100,13 @@ module system_top (
   output            spim1_mosi,
   input             spim1_miso,
 
+  // iic interface
+
+  inout             scl,
+  inout             sda,
+  output            ga0,
+  output            ga1,
+
   // hps-uart
 
   input             uart0_rx,
@@ -153,6 +160,11 @@ module system_top (
   wire    [ 31:0]   sys_gpio_i;
   wire    [ 31:0]   sys_gpio_o;
 
+  wire              i2c0_out_data;
+  wire              i2c0_sda;
+  wire              i2c0_out_clk;
+  wire              i2c0_scl_in_clk;
+
   // defaults
 
   assign vga_blank_n = 1'b1;
@@ -166,6 +178,11 @@ module system_top (
   assign ad9361_resetb = sys_gpio_o[4];
   assign ad9361_en_agc = sys_gpio_o[3];
   assign ad9361_sync = sys_gpio_o[2];
+  assign ga0 = 1'b0;
+  assign ga1 = 1'b0;
+
+ ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl));
+ ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda));
 
   // instantiations
 
@@ -236,6 +253,10 @@ module system_top (
     .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
     .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
     .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+    .sys_hps_i2c0_out_data(i2c0_out_data),
+    .sys_hps_i2c0_sda(i2c0_sda),
+    .sys_hps_i2c0_clk_clk(i2c0_out_clk),
+    .sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk),
     .sys_hps_memory_mem_a (ddr3_a),
     .sys_hps_memory_mem_ba (ddr3_ba),
     .sys_hps_memory_mem_ck (ddr3_ck_p),
@@ -266,7 +287,9 @@ module system_top (
     .vga_out_data_vid_h_sync (vga_hsync),
     .vga_out_data_vid_f (),
     .vga_out_data_vid_h (),
-    .vga_out_data_vid_v ());
+    .vga_out_data_vid_v (),
+    .vga_if_vid_v ()
+	 );
 
 endmodule
 

projects/common/c5soc/c5soc_system_assign.tcl

@@ -444,6 +444,81 @@ set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n
 set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst
 set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout
 
+# ddr3 pin locations (quartus critical warnings)
+
+set_location_assignment PIN_F26   -to ddr3_a[0]
+set_location_assignment PIN_G30   -to ddr3_a[1]
+set_location_assignment PIN_F28   -to ddr3_a[2]
+set_location_assignment PIN_F30   -to ddr3_a[3]
+set_location_assignment PIN_J25   -to ddr3_a[4]
+set_location_assignment PIN_J27   -to ddr3_a[5]
+set_location_assignment PIN_F29   -to ddr3_a[6]
+set_location_assignment PIN_E28   -to ddr3_a[7]
+set_location_assignment PIN_H27   -to ddr3_a[8]
+set_location_assignment PIN_G26   -to ddr3_a[9]
+set_location_assignment PIN_D29   -to ddr3_a[10]
+set_location_assignment PIN_C30   -to ddr3_a[11]
+set_location_assignment PIN_B30   -to ddr3_a[12]
+set_location_assignment PIN_C29   -to ddr3_a[13]
+set_location_assignment PIN_H25   -to ddr3_a[14]
+set_location_assignment PIN_E29   -to ddr3_ba[0]
+set_location_assignment PIN_J24   -to ddr3_ba[1]
+set_location_assignment PIN_J23   -to ddr3_ba[2]
+set_location_assignment PIN_E27   -to ddr3_cas_n
+set_location_assignment PIN_M23   -to ddr3_ck_p
+set_location_assignment PIN_L23   -to ddr3_ck_n
+set_location_assignment PIN_L29   -to ddr3_cke
+set_location_assignment PIN_H24   -to ddr3_cs_n
+set_location_assignment PIN_K28   -to ddr3_dm[0]
+set_location_assignment PIN_M28   -to ddr3_dm[1]
+set_location_assignment PIN_R28   -to ddr3_dm[2]
+set_location_assignment PIN_W30   -to ddr3_dm[3]
+set_location_assignment PIN_K23   -to ddr3_dq[0]
+set_location_assignment PIN_K22   -to ddr3_dq[1]
+set_location_assignment PIN_H30   -to ddr3_dq[2]
+set_location_assignment PIN_G28   -to ddr3_dq[3]
+set_location_assignment PIN_L25   -to ddr3_dq[4]
+set_location_assignment PIN_L24   -to ddr3_dq[5]
+set_location_assignment PIN_J30   -to ddr3_dq[6]
+set_location_assignment PIN_J29   -to ddr3_dq[7]
+set_location_assignment PIN_K26   -to ddr3_dq[8]
+set_location_assignment PIN_L26   -to ddr3_dq[9]
+set_location_assignment PIN_K29   -to ddr3_dq[10]
+set_location_assignment PIN_K27   -to ddr3_dq[11]
+set_location_assignment PIN_M26   -to ddr3_dq[12]
+set_location_assignment PIN_M27   -to ddr3_dq[13]
+set_location_assignment PIN_L28   -to ddr3_dq[14]
+set_location_assignment PIN_M30   -to ddr3_dq[15]
+set_location_assignment PIN_U26   -to ddr3_dq[16]
+set_location_assignment PIN_T26   -to ddr3_dq[17]
+set_location_assignment PIN_N29   -to ddr3_dq[18]
+set_location_assignment PIN_N28   -to ddr3_dq[19]
+set_location_assignment PIN_P26   -to ddr3_dq[20]
+set_location_assignment PIN_P27   -to ddr3_dq[21]
+set_location_assignment PIN_N27   -to ddr3_dq[22]
+set_location_assignment PIN_R29   -to ddr3_dq[23]
+set_location_assignment PIN_P24   -to ddr3_dq[24]
+set_location_assignment PIN_P25   -to ddr3_dq[25]
+set_location_assignment PIN_T29   -to ddr3_dq[26]
+set_location_assignment PIN_T28   -to ddr3_dq[27]
+set_location_assignment PIN_R27   -to ddr3_dq[28]
+set_location_assignment PIN_R26   -to ddr3_dq[29]
+set_location_assignment PIN_V30   -to ddr3_dq[30]
+set_location_assignment PIN_W29   -to ddr3_dq[31]
+set_location_assignment PIN_N18   -to ddr3_dqs_p[0]
+set_location_assignment PIN_M19   -to ddr3_dqs_n[0]
+set_location_assignment PIN_N25   -to ddr3_dqs_p[1]
+set_location_assignment PIN_N24   -to ddr3_dqs_n[1]
+set_location_assignment PIN_R19   -to ddr3_dqs_p[2]
+set_location_assignment PIN_R18   -to ddr3_dqs_n[2]
+set_location_assignment PIN_R22   -to ddr3_dqs_p[3]
+set_location_assignment PIN_R21   -to ddr3_dqs_n[3]
+set_location_assignment PIN_H28   -to ddr3_odt
+set_location_assignment PIN_D30   -to ddr3_ras_n
+set_location_assignment PIN_P30   -to ddr3_reset_n
+set_location_assignment PIN_C28   -to ddr3_we_n
+set_location_assignment PIN_D27   -to ddr3_rzq
+
 # globals
 
 set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON

projects/common/c5soc/c5soc_system_qsys.tcl

@@ -43,6 +43,8 @@ set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
 set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
 set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
 set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
+set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
+set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
 set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
 set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
 set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
@@ -104,6 +106,12 @@ add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
 add_connection sys_clk.clk sys_hps.h2f_axi_clock
 add_connection sys_clk.clk sys_hps.f2h_axi_clock
 add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
+add_interface sys_hps_i2c0 conduit end
+set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
+add_interface sys_hps_i2c0_clk clock source
+set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
+add_interface sys_hps_i2c0_scl_in clock sink
+set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
 
 # cpu/hps handling