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library/axi_jesd_xcvr: interface name matching

main
Rejeesh Kutty 2015-07-07 10:21:53 -04:00
parent b106b8a8f4
commit c1fcbeec8e
3 changed files with 12 additions and 12 deletions
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4
library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc
View File

@ -2,10 +2,10 @@
set_false_path -from [get_registers *preset*] -to [get_registers *rst*] set_false_path -from [get_registers *preset*] -to [get_registers *rst*]
set_false_path -from [get_registers *up_rx_sysref*] -to [get_registers *rx_sysref_m1*] set_false_path -from [get_registers *up_rx_sysref*] -to [get_registers *rx_sysref_m1*]
set_false_path -from [get_registers *up_rx_sync*] -to [get_registers *rx_sync_m1*] set_false_path -from [get_registers *up_rx_sync*] -to [get_registers *rx_sync_m1*]
set_false_path -from [get_registers *rx_sync*] -to [get_registers *up_rx_status_m1*] set_false_path -from [get_registers *rx_ip_sync*] -to [get_registers *up_rx_status_m1*]
set_false_path -from [get_registers *rx_status*] -to [get_registers *up_rx_status_m1*] set_false_path -from [get_registers *rx_status*] -to [get_registers *up_rx_status_m1*]
set_false_path -from [get_registers *up_tx_sysref*] -to [get_registers *tx_sysref_m1*] set_false_path -from [get_registers *up_tx_sysref*] -to [get_registers *tx_sysref_m1*]
set_false_path -from [get_registers *up_tx_sync*] -to [get_registers *tx_ip_sync_m1*] set_false_path -from [get_registers *up_tx_sync*] -to [get_registers *tx_ip_sync_m1*]
set_false_path -from [get_registers *tx_ip_sync*] -to [get_registers *up_tx_status_m1*] set_false_path -from [get_registers *tx_sync*] -to [get_registers *up_tx_status_m1*]
set_false_path -from [get_registers *tx_status*] -to [get_registers *up_tx_status_m1*] set_false_path -from [get_registers *tx_status*] -to [get_registers *up_tx_status_m1*]

16
library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
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@ -36,14 +36,14 @@ set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
add_parameter PCORE_NUM_OF_TX_LANES INTEGER 0 add_parameter PCORE_NUM_OF_TX_LANES INTEGER 0
set_parameter_property PCORE_NUM_OF_TX_LANES DEFAULT_VALUE 0 set_parameter_property PCORE_NUM_OF_TX_LANES DEFAULT_VALUE 4
set_parameter_property PCORE_NUM_OF_TX_LANES DISPLAY_NAME PCORE_NUM_OF_TX_LANES set_parameter_property PCORE_NUM_OF_TX_LANES DISPLAY_NAME PCORE_NUM_OF_TX_LANES
set_parameter_property PCORE_NUM_OF_TX_LANES TYPE INTEGER set_parameter_property PCORE_NUM_OF_TX_LANES TYPE INTEGER
set_parameter_property PCORE_NUM_OF_TX_LANES UNITS None set_parameter_property PCORE_NUM_OF_TX_LANES UNITS None
set_parameter_property PCORE_NUM_OF_TX_LANES HDL_PARAMETER true set_parameter_property PCORE_NUM_OF_TX_LANES HDL_PARAMETER true
add_parameter PCORE_NUM_OF_RX_LANES INTEGER 0 add_parameter PCORE_NUM_OF_RX_LANES INTEGER 0
set_parameter_property PCORE_NUM_OF_RX_LANES DEFAULT_VALUE 0 set_parameter_property PCORE_NUM_OF_RX_LANES DEFAULT_VALUE 4
set_parameter_property PCORE_NUM_OF_RX_LANES DISPLAY_NAME PCORE_NUM_OF_RX_LANES set_parameter_property PCORE_NUM_OF_RX_LANES DISPLAY_NAME PCORE_NUM_OF_RX_LANES
set_parameter_property PCORE_NUM_OF_RX_LANES TYPE INTEGER set_parameter_property PCORE_NUM_OF_RX_LANES TYPE INTEGER
set_parameter_property PCORE_NUM_OF_RX_LANES UNITS None set_parameter_property PCORE_NUM_OF_RX_LANES UNITS None
@ -95,10 +95,10 @@ set_interface_property if_rx_rst associatedClock if_rx_clk
add_interface_port if_rx_rst rx_rst reset Output 1 add_interface_port if_rx_rst rx_rst reset Output 1
ad_alt_intf signal rx_ext_sysref input 1 ad_alt_intf signal rx_ext_sysref input 1
ad_alt_intf signal rx_sysref output 1 ad_alt_intf signal rx_sysref output 1 export
ad_alt_intf signal rx_ip_sync input 1 ad_alt_intf signal rx_ip_sync input 1 export
ad_alt_intf signal rx_sync output 1 ad_alt_intf signal rx_sync output 1
ad_alt_intf signal rx_status input PCORE_NUM_OF_RX_LANES ad_alt_intf signal rx_status input PCORE_NUM_OF_RX_LANES rx_ready
add_interface if_tx_clk clock end add_interface if_tx_clk clock end
add_interface_port if_tx_clk tx_clk clk Input 1 add_interface_port if_tx_clk tx_clk clk Input 1
@ -108,10 +108,10 @@ set_interface_property if_tx_rst associatedClock if_tx_clk
add_interface_port if_tx_rst tx_rst reset Output 1 add_interface_port if_tx_rst tx_rst reset Output 1
ad_alt_intf signal tx_ext_sysref input 1 ad_alt_intf signal tx_ext_sysref input 1
ad_alt_intf signal tx_sysref output 1 ad_alt_intf signal tx_sysref output 1 export
ad_alt_intf signal tx_sync input 1 ad_alt_intf signal tx_sync input 1
ad_alt_intf signal tx_ip_sync output 1 ad_alt_intf signal tx_ip_sync output 1 export
ad_alt_intf signal tx_status input PCORE_NUM_OF_TX_LANES ad_alt_intf signal tx_status input PCORE_NUM_OF_TX_LANES tx_ready

4
library/common/up_xcvr.v
View File

@ -296,9 +296,9 @@ module up_xcvr (
up_tx_status_m1 <= 'd0; up_tx_status_m1 <= 'd0;
up_tx_status <= 'd0; up_tx_status <= 'd0;
end else begin end else begin
up_rx_status_m1 <= {rx_sync, rx_status}; up_rx_status_m1 <= {rx_ip_sync, rx_status};
up_rx_status <= up_rx_status_m1; up_rx_status <= up_rx_status_m1;
up_tx_status_m1 <= {tx_ip_sync, tx_status}; up_tx_status_m1 <= {tx_sync, tx_status};
up_tx_status <= up_tx_status_m1; up_tx_status <= up_tx_status_m1;
end end
end end