ad9361/sw- current sw requires clock edge swap

2017-07-31 14:48:25 -04:00 · 2017-07-31 14:48:25 -04:00 · c1e990b575
parent 0bc5a80c0c
commit c1e990b575
1 changed files with 1 additions and 1 deletions
--- a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
@ -274,7 +274,7 @@ module axi_ad9361_cmos_if #(
  // dac-tx interface

  always @(posedge clk) begin
-    tx_clk_p <= {dac_clksel, ~dac_clksel};
+    tx_clk_p <= {~dac_clksel, dac_clksel};
  end

  always @(posedge clk) begin