AD9434: Zed porting and documentation (#1210)
cristianmihaipopa
GitHub
parent
9f2a03f29d
commit
c1e0698719
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@ -24,6 +24,7 @@ HDL Reference Designs
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AD719X-ASDZ <projects/ad719x_asdz/index>
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AD7616-SDZ <projects/ad7616_sdz/index>
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AD9081-FMCA-EBZ/AD9082-FMCA-EBZ <projects/ad9081_fmca_ebz/index>
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AD9434-FMC <projects/ad9434_fmc/index>
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AD9783-EBZ <projects/ad9783_ebz/index>
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ADAQ7980-SDZ <projects/adaq7980_sdz/index>
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@ -44,4 +45,4 @@ HDL Reference Designs
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HDL libraries and projects for various reference design and prototyping systems.
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This repository contains HDL code (Verilog or VHDL) and the required Tcl scripts
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to create and build a specific FPGA example design using Xilinx and/or Intel tool
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chain.
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chain.
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.. _ad9434_fmc:
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AD9434-FMC HDL project
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================================================================================
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Overview
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-------------------------------------------------------------------------------
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The :adi:`AD9434` is a 12-bit monolithic sampling analog-to-digital converter
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(ADC) optimized for high performance, low power, and ease of use. The part
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operates at up to a 500 MSPS conversion rate and is optimized for outstanding
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dynamic performance in wideband carrier and broadband systems. All necessary
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functions, including a sample-and-hold and voltage reference, are included on
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the chip to provide a complete signal conversion solution. This reference
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design includes a data capture interface and the external DDR-DRAM interface
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for sample storage. It allows programming the device and monitoring its internal
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status registers. The board also provides other options to drive the clock and
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analog inputs of the ADC.
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-AD9434`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD9434`
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Supported carriers
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-------------------------------------------------------------------------------
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.. list-table::
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:widths: 35 35 30
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:header-rows: 1
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* - Evaluation board
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- Carrier
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- FMC slot
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* - :adi:`EVAL-AD9434-FMC-500EBZ <EVAL-AD9434>`
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- :xilinx:`ZC706`
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- FMC LPC
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* -
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>`
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- FMC LPC
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Block design
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-------------------------------------------------------------------------------
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. image:: ad9434_fmc_block_diagram.svg
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:width: 800
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:align: center
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:alt: AD9434-FMC/ZC706/ZED block diagram
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Clock scheme
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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There are multiple ways to configure the clock source for :adi:`AD9434`.
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In this section is presented a guide on how to rework the board to the desired
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user clock circuitry. Below is a table on what components are needed to install
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or uninstall on the evaluation board.
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==================== ======================================== ================
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Clock Configuration Install Uninstall
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==================== ======================================== ================
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Ext. Signal Gen. as it is as it is
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Oscillator R209, P1(shunt) ---
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LVPECL R208, R307, R308, C300, C311, C304, C305 C209, C210
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LVDS R208, C306, C307 C209, C210, R311
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==================== ======================================== ================
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For LVPECL and LVDS configurations, appropriate charge pump filter circuit
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values are necessary to have an optimized clock buffer performance from
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:adi:`AD9517-4`.
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL(see more at :ref:`architecture`).
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==================== ===============
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Instance Zynq/Microblaze
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==================== ===============
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axi_ad9434 0x44A0_0000
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axi_ad9434_dma 0x44A3_0000
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==================== ===============
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PS
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- SPI 0
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- AD9517
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- 1
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* - PS
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- SPI 0
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- AD9434BCPZ
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- 0
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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================ === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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================ === ========== ===========
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axi_ad9783_dma 13 57 89
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================ === ========== ===========
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These are the board-specific interrupts
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(found in :git-hdl:`here <projects/ad9434_fmc/common/ad9434_bd.tcl>`).
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository.
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Then go to the project location (**projects/ad9434_fmc/carrier**) and run the
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make command by typing in your command prompt (this example is for
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:xilinx:`ZC706`):
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**Linux/Cygwin/WSL**
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.. code-block::
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user@analog:~$ cd hdl/projects/ad9434_fmc/zc706
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user@analog:~/hdl/projects/ad9434_fmc/zc706$ make
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A more comprehensive build guide can be found in the :ref:`build_hdl` user
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guide.
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Resources
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-------------------------------------------------------------------------------
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Systems related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Here you can find the quick start guides available for these evaluation boards:
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.. list-table::
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:widths: 20 10
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:header-rows: 1
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* - Evaluation board
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- Zynq-7000
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* - AD9434-FMC
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- :dokuwiki:`ZC706 <resources/fpga/xilinx/fmc/ad9434>`
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheets: :adi:`AD9434`
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- :dokuwiki:`EVAL-AD9434 user guide <resources/eval/ad9434fmc-500ebz>`
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`AD9434-FMC HDL project source code <projects/ad9434_fmc>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_AD9434
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- :git-hdl:`library/axi_ad9434 <library/axi_ad9434>`
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- ---
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <library/axi_dmac>`
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- :ref:`here <axi_dmac>`
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx <library/axi_ad9434>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_SPDIF_TX
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- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
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- ---
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* - AXI_SYSID
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- :git-hdl:`library/axi_sysid <library/axi_sysid>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - SYSID_ROM
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- :git-hdl:`library/sysid_rom <library/sysid_rom>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-linux:`Linux device tree zynq-zc706-adv7511-ad9434-fmc-500ebz.dts <arch/arm/boot/dts/zynq-zc706-adv7511-ad9434-fmc-500ebz.dts>`
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- :git-linux:`Linux driver ad9467.c <drivers/iio/adc/ad9467.c>`
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(used for AD9434-FMC as well)
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.. include:: ../common/more_information.rst
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.. include:: ../common/support.rst
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@ -0,0 +1,26 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad9434_fmc_zed
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M_DEPS += ../common/ad9434_spi.v
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M_DEPS += ../common/ad9434_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_ad9434
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_i2c_mixer
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include ../../scripts/project-xilinx.mk
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@ -0,0 +1,17 @@
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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source ../common/ad9434_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file
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@ -0,0 +1,45 @@
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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ad9434
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_p] ; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_n] ; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[0]] ; ## D17 FMC_LA13_P IO_L4P_T0_34
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set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[0]] ; ## D18 FMC_LA13_N IO_L4N_T0_34
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set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[1]] ; ## H16 FMC_LA11_P IO_L5P_T0_34
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set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[2]] ; ## G15 FMC_LA12_P IO_L18P_T2_34
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[2]] ; ## G16 FMC_LA12_N IO_L18N_T2_34
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set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[3]] ; ## D14 FMC_LA09_P IO_L17P_T2_34
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set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[3]] ; ## D15 FMC_LA09_N IO_L17N_T2_34
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set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[4]] ; ## C14 FMC_LA10_P IO_L22P_T3_34
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set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[4]] ; ## C15 FMC_LA10_N IO_L22N_T3_34
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set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[5]] ; ## H13 FMC_LA07_P IO_L21P_T3_DQS_34
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set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[5]] ; ## H14 FMC_LA07_N IO_L21N_T3_DQS_34
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[6]] ; ## G12 FMC_LA08_P IO_L8P_T1_34
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set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[6]] ; ## G13 FMC_LA08_N IO_L8N_T1_34
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[7]] ; ## D11 FMC_LA05_P IO_L7P_T1_34
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[7]] ; ## D12 FMC_LA05_N IO_L7N_T1_34
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set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[8]] ; ## C10 FMC_LA06_P IO_L10P_T1_34
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[8]] ; ## C11 FMC_LA06_N IO_L10N_T1_34
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[9]] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34
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set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[9]] ; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34
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set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[10]] ; ## G9 FMC_LA03_P IO_L16P_T2_34
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set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[10]] ; ## G10 FMC_LA03_N IO_L16N_T2_34
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[11]] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[11]] ; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34
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#adc
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_p] ; ## H7 FMC_LA02_P IO_L20P_T3_34
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_n] ; ## H8 FMC_LA02_N IO_L20N_T3_34
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#spi
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set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G36 FMC_LA33_P IO_L18P_T2_AD13P_35
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set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## G37 FMC_LA33_N IO_L18N_T2_AD13N_35
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set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_dio] ; ## H37 FMC_LA32_P IO_L15P_T2_DQS_AD12P_35
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set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## H38 FMC_LA32_N IO_L15N_T2_DQS_AD12N_35
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@ -0,0 +1,18 @@
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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project ad9434_fmc_zed
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adi_project_files ad9434_fmc_zed [list \
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"../common/ad9434_spi.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
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adi_project_run ad9434_fmc_zed
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@ -0,0 +1,226 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [31:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [15:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_sdata_out,
|
||||
input i2s_sdata_in,
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
inout [ 1:0] iic_mux_scl,
|
||||
inout [ 1:0] iic_mux_sda,
|
||||
|
||||
input otg_vbusoc,
|
||||
|
||||
input adc_clk_p,
|
||||
input adc_clk_n,
|
||||
input [11:0] adc_data_p,
|
||||
input [11:0] adc_data_n,
|
||||
input adc_or_p,
|
||||
input adc_or_n,
|
||||
|
||||
output spi_csn_clk,
|
||||
output spi_csn_adc,
|
||||
output spi_sclk,
|
||||
inout spi_dio
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
wire spi_miso;
|
||||
wire spi_mosi;
|
||||
|
||||
assign gpio_i[63:32] = gpio_o[63:32];
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH (32)
|
||||
) i_iobuf (
|
||||
.dio_t (gpio_t[31:0]),
|
||||
.dio_i (gpio_o[31:0]),
|
||||
.dio_o (gpio_i[31:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH (2)
|
||||
) i_iic_mux_scl (
|
||||
.dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}),
|
||||
.dio_i (iic_mux_scl_o_s),
|
||||
.dio_o (iic_mux_scl_i_s),
|
||||
.dio_p (iic_mux_scl));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH (2)
|
||||
) i_iic_mux_sda (
|
||||
.dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
||||
.dio_i (iic_mux_sda_o_s),
|
||||
.dio_o (iic_mux_sda_i_s),
|
||||
.dio_p (iic_mux_sda));
|
||||
|
||||
ad9434_spi i_spi (
|
||||
.spi_csn({spi_csn_clk, spi_csn_adc}),
|
||||
.spi_clk(spi_sclk),
|
||||
.spi_mosi(spi_mosi),
|
||||
.spi_miso(spi_miso),
|
||||
.spi_sdio(spi_dio));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
|
||||
.spdif (spdif),
|
||||
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
|
||||
.adc_clk_p(adc_clk_p),
|
||||
.adc_clk_n(adc_clk_n),
|
||||
.adc_data_p(adc_data_p),
|
||||
.adc_data_n(adc_data_n),
|
||||
.adc_or_p(adc_or_p),
|
||||
.adc_or_n(adc_or_n),
|
||||
|
||||
.spi0_clk_i (spi_sclk),
|
||||
.spi0_clk_o (spi_sclk),
|
||||
.spi0_csn_0_o (spi_csn_adc),
|
||||
.spi0_csn_1_o (spi_csn_clk),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (spi_mosi),
|
||||
.spi0_sdo_o (spi_mosi),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o ());
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue