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account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores

main
Nick Pillitteri 2022-03-18 17:10:26 -04:00 committed by Adrian Costina
parent 0d9e9e42c0
commit c1721e18dd
27 changed files with 146 additions and 101 deletions
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9
library/axi_ad5766/axi_ad5766_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad5766
adi_ip_files axi_ad5766 [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
@ -20,9 +22,9 @@ adi_ip_properties axi_ad5766
adi_init_bd_tcl
adi_ip_bd axi_ad5766 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
@ -61,4 +63,3 @@ adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]

8
library/axi_ad6676/axi_ad6676_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad6676
adi_ip_files axi_ad6676 [list \
"axi_ad6676.v" ]
@ -12,9 +14,9 @@ adi_ip_properties axi_ad6676
adi_init_bd_tcl
adi_ip_bd axi_ad6676 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_adc:1.0 \
]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

15
library/axi_ad7616/axi_ad7616_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad7616
adi_ip_files axi_ad7616 [list \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
@ -16,14 +18,13 @@ adi_ip_properties axi_ad7616
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7616} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:spi_engine_execution:1.0 \
analog.com:user:axi_spi_engine:1.0 \
analog.com:user:spi_engine_offload:1.0 \
analog.com:user:spi_engine_interconnect:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:spi_engine_execution:1.0 \
analog.com:$VIVADO_IP_LIBRARY:axi_spi_engine:1.0 \
analog.com:$VIVADO_IP_LIBRARY:spi_engine_offload:1.0 \
analog.com:$VIVADO_IP_LIBRARY:spi_engine_interconnect:1.0 \
]
set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i]
ipx::save_core [ipx::current_core]

9
library/axi_ad9144/axi_ad9144_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad9144
adi_ip_files axi_ad9144 [list \
"axi_ad9144.v" ]
@ -14,9 +16,9 @@ adi_ip_bd axi_ad9144 "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9144} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_dac:1.0 \
]
adi_set_ports_dependency "dac_valid_2" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_valid_3" "QUAD_OR_DUAL_N == 1"
@ -34,4 +36,3 @@ adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]

8
library/axi_ad9152/axi_ad9152_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad9152
adi_ip_files axi_ad9152 [list \
"axi_ad9152.v" ]
@ -12,9 +14,9 @@ adi_ip_properties axi_ad9152
adi_init_bd_tcl
adi_ip_bd axi_ad9152 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_dac:1.0 \
]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]

8
library/axi_ad9250/axi_ad9250_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad9250
adi_ip_files axi_ad9250 [list \
"axi_ad9250.v" ]
@ -12,9 +14,9 @@ adi_ip_properties axi_ad9250
adi_init_bd_tcl
adi_ip_bd axi_ad9250 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_adc:1.0 \
]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

8
library/axi_ad9680/axi_ad9680_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_ad9680
adi_ip_files axi_ad9680 [list \
"axi_ad9680.v" ]
@ -12,9 +14,9 @@ adi_ip_properties axi_ad9680
adi_init_bd_tcl
adi_ip_bd axi_ad9680 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_adc:1.0 \
]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

9
library/axi_adc_decimate/axi_adc_decimate_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_adc_decimate
adi_ip_files axi_adc_decimate [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
@ -20,12 +22,11 @@ adi_ip_properties axi_adc_decimate
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adc_decimate} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_cic:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cic:1.0 \
]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]

9
library/axi_adrv9001/axi_adrv9001_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_adrv9001
adi_ip_files axi_adrv9001 [list \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
@ -58,9 +60,9 @@ adi_ip_properties axi_adrv9001
adi_init_bd_tcl
adi_ip_bd axi_adrv9001 "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set cc [ipx::current_core]
@ -113,4 +115,3 @@ adi_add_auto_fpga_spec_params
ipx::create_xgui_files $cc
ipx::save_core $cc

10
library/axi_dmac/axi_dmac_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_dmac
adi_ip_files axi_dmac [list \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
@ -45,10 +47,10 @@ adi_ip_bd axi_dmac "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dmac} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_axis_fifo:1.0 \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set_property display_name "ADI AXI DMA Controller" [ipx::current_core]
set_property description "ADI AXI DMA Controller" [ipx::current_core]

10
library/axi_laser_driver/axi_laser_driver_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_laser_driver
adi_ip_files axi_laser_driver [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
@ -16,10 +18,10 @@ adi_ip_ttcl axi_laser_driver "../axi_pulse_gen/axi_pulse_gen_constr.ttcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_laser_driver} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
analog.com:user:axi_pulse_gen:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
analog.com:$VIVADO_IP_LIBRARY:axi_pulse_gen:1.0 \
]
set cc [ipx::current_core]

8
library/axi_pulse_gen/axi_pulse_gen_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_pulse_gen
adi_ip_files axi_pulse_gen [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -16,9 +18,9 @@ adi_ip_files axi_pulse_gen [list \
adi_ip_properties axi_pulse_gen
adi_ip_ttcl axi_pulse_gen "axi_pulse_gen_constr.ttcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set cc [ipx::current_core]

8
library/axi_pwm_gen/axi_pwm_gen_ip.tcl
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@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_pwm_gen
adi_ip_files axi_pwm_gen [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -18,9 +20,9 @@ adi_ip_ttcl axi_pwm_gen "axi_pwm_gen_constr.ttcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set cc [ipx::current_core]

10
library/data_offload/data_offload_ip.tcl
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@ -1,6 +1,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create data_offload
adi_ip_files data_offload [list \
"data_offload_sv.ttcl" \
@ -18,10 +20,10 @@ adi_ip_properties data_offload
adi_ip_ttcl data_offload "data_offload_constr.ttcl"
adi_ip_sim_ttcl data_offload "data_offload_sv.ttcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
analog.com:user:util_axis_fifo_asym:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo_asym:1.0 \
]
set_property display_name "ADI Data Offload Controller" [ipx::current_core]
set_property description "ADI Data Offload Controller" [ipx::current_core]

8
library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
View File

@ -45,6 +45,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_jesd204_common
add_files -fileset [get_filesets sources_1] [list \
@ -56,9 +58,9 @@ add_files -fileset [get_filesets sources_1] [list \
adi_ip_properties_lite axi_jesd204_common
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set_property display_name "ADI AXI JESD204B Common Library" [ipx::current_core]
set_property description "ADI AXI JESD204B Common Library" [ipx::current_core]
set_property hide_in_gui {1} [ipx::current_core]

8
library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
View File

@ -45,6 +45,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_jesd204_rx
adi_ip_files axi_jesd204_rx [list \
"../../common/up_axi.v" \
@ -66,9 +68,9 @@ set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
-filter {NAME =~ *synthesis*}]]
adi_ip_add_core_dependencies { \
analog.com:user:axi_jesd204_common:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:axi_jesd204_common:1.0 \
]
set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core]
set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core]

8
library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
View File

@ -45,6 +45,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_jesd204_tx
adi_ip_files axi_jesd204_tx [list \
"../../common/up_axi.v" \
@ -64,9 +66,9 @@ set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
-filter {NAME =~ *synthesis*}]]
adi_ip_add_core_dependencies { \
analog.com:user:axi_jesd204_common:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:axi_jesd204_common:1.0 \
]
set_property display_name "ADI JESD204C Transmit AXI Interface" [ipx::current_core]
set_property description "ADI JESD204B Transmit AXI Interface" [ipx::current_core]

10
library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
View File

@ -45,6 +45,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create jesd204_rx
adi_ip_files jesd204_rx [list \
"jesd204_rx_lane.v" \
@ -71,10 +73,10 @@ adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl"
adi_ip_ttcl jesd204_rx "jesd204_rx_ooc.ttcl"
adi_ip_bd jesd204_rx "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:jesd204_common:1.0 \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:jesd204_common:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set_property display_name "ADI JESD204 Receive" [ipx::current_core]
set_property description "ADI JESD204 Receive" [ipx::current_core]

10
library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
View File

@ -45,6 +45,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create jesd204_tx
adi_ip_files jesd204_tx [list \
"jesd204_tx_lane.v" \
@ -64,10 +66,10 @@ adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
adi_ip_ttcl jesd204_tx "jesd204_tx_ooc.ttcl"
adi_ip_bd jesd204_tx "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:jesd204_common:1.0 \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:jesd204_common:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set_property display_name "ADI JESD204 Transmit" [ipx::current_core]
set_property description "ADI JESD204 Transmit" [ipx::current_core]

10
library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
View File

@ -3,6 +3,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_spi_engine
adi_ip_files axi_spi_engine [list \
"$ad_hdl_dir/library/common/up_axi.v" \
@ -15,10 +17,10 @@ adi_ip_files axi_spi_engine [list \
adi_ip_properties axi_spi_engine
adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_axis_fifo:1.0 \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi} [ipx::current_core]

8
library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
View File

@ -1,6 +1,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create spi_engine_offload
adi_ip_files spi_engine_offload [list \
"spi_engine_offload_constr.ttcl" \
@ -15,9 +17,9 @@ set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi
# Remove all inferred interfaces
ipx::remove_all_bus_interface [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
## Interface definitions

10
library/util_adcfifo/util_adcfifo_ip.tcl
View File

@ -3,6 +3,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create util_adcfifo
adi_ip_files util_adcfifo [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
@ -13,9 +15,9 @@ adi_ip_files util_adcfifo [list \
adi_ip_properties_lite util_adcfifo
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
@ -23,5 +25,3 @@ ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_c
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]

8
library/util_axis_fifo/util_axis_fifo_ip.tcl
View File

@ -2,6 +2,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create util_axis_fifo
adi_ip_files util_axis_fifo [list \
"util_axis_fifo_address_generator.v" \
@ -12,9 +14,9 @@ adi_ip_files util_axis_fifo [list \
adi_ip_properties_lite util_axis_fifo
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set_property display_name "ADI AXI Stream FIFO" [ipx::current_core]
set_property description "ADI AXI Stream FIFO" [ipx::current_core]

10
library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl
View File

@ -2,6 +2,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create util_axis_fifo_asym
adi_ip_files util_axis_fifo_asym [list \
"util_axis_fifo_asym.v" \
@ -11,10 +13,10 @@ adi_ip_properties_lite util_axis_fifo_asym
set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
analog.com:user:util_axis_fifo:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
]
adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \

10
library/util_fifo2axi_bridge/util_fifo2axi_bridge_ip.tcl
View File

@ -1,6 +1,8 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create util_fifo2axi_bridge
adi_ip_files util_fifo2axi_bridge [list \
"util_fifo2axi_bridge_constr.xdc" \
@ -9,10 +11,10 @@ adi_ip_files util_fifo2axi_bridge [list \
adi_ip_properties_lite util_fifo2axi_bridge
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
analog.com:user:util_axis_fifo_asym:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo_asym:1.0 \
]
set_property display_name "ADI FIFO to AXI4 bridge" [ipx::current_core]
set_property description "Bridge between a FIFO READ/WRITE interface and an AXI4 Memory Mapped interface" [ipx::current_core]

9
library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl
View File

@ -2,6 +2,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_xcvrlb
adi_ip_files axi_xcvrlb [list \
"$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \
@ -17,9 +19,9 @@ adi_ip_properties_lite axi_xcvrlb
adi_init_bd_tcl
adi_ip_bd axi_xcvrlb "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
ipx::remove_all_bus_interface [ipx::current_core]
@ -65,4 +67,3 @@ set_property range {1024} [ipx::get_address_blocks axi_lite \
adi_add_auto_fpga_spec_params
ipx::save_core [ipx::current_core]

9
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -3,6 +3,8 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create util_adxcvr
adi_ip_files util_adxcvr [list \
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
@ -19,9 +21,9 @@ adi_ip_bd util_adxcvr "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_xcvr} [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set cc [ipx::current_core]
# Arrange GUI page layout
@ -1308,4 +1310,3 @@ set_property -dict [list \
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]