From c16ebb3cefa1979c10832471484658769de41c72 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 2 Mar 2022 15:56:41 +0000 Subject: [PATCH] common/vcu128: Add HBM clocking support 450MHz The HBM interfacing core requires a 450MHz clock, make it part of the base design. The clock can't be obtained from the DDR controller so a clock wizard is used instead. --- projects/common/vcu128/vcu128_system_bd.tcl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/projects/common/vcu128/vcu128_system_bd.tcl b/projects/common/vcu128/vcu128_system_bd.tcl index fce01e8e0..059d2a863 100644 --- a/projects/common/vcu128/vcu128_system_bd.tcl +++ b/projects/common/vcu128/vcu128_system_bd.tcl @@ -74,6 +74,15 @@ ad_ip_instance proc_sys_reset sys_250m_rstgen ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1 ad_ip_instance proc_sys_reset sys_500m_rstgen ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1 +ad_ip_instance proc_sys_reset sys_hbm_rstgen +ad_ip_parameter sys_hbm_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# Clock for HBM +ad_ip_instance clk_wiz hbm_clk_wiz [ list \ + PRIMITIVE {Auto} \ + PRIM_IN_FREQ {100} \ + CLKOUT1_REQUESTED_OUT_FREQ {450} \ +] # instance: ddr4 # @@ -150,6 +159,7 @@ ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_ ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_250m_rstgen/ext_reset_in ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_500m_rstgen/ext_reset_in +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_hbm_rstgen/ext_reset_in ad_connect sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk ad_connect sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1 @@ -160,6 +170,8 @@ ad_connect sys_250m_clk axi_ddr_cntrl/addn_ui_clkout2 ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk ad_connect sys_500m_clk axi_ddr_cntrl/addn_ui_clkout3 ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk +ad_connect sys_hbm_clk hbm_clk_wiz/clk_out1 +ad_connect sys_hbm_clk sys_hbm_rstgen/slowest_sync_clk ad_connect sys_cpu_reset sys_rstgen/peripheral_reset ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset @@ -172,6 +184,7 @@ ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn set sys_cpu_clk [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1] set sys_dma_clk [get_bd_nets sys_250m_clk] set sys_iodelay_clk [get_bd_nets sys_500m_clk] +set sys_hbm_clk [get_bd_pins hbm_clk_wiz/clk_out1] set sys_cpu_reset [get_bd_nets sys_cpu_reset] set sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn] @@ -179,6 +192,12 @@ set sys_dma_reset [get_bd_nets sys_250m_reset] set sys_dma_resetn [get_bd_nets sys_250m_resetn] set sys_iodelay_reset [get_bd_nets sys_500m_reset] set sys_iodelay_resetn [get_bd_nets sys_500m_resetn] +set sys_hbm_reset [get_bd_pins sys_hbm_rstgen/peripheral_reset] +set sys_hbm_resetn [get_bd_pins sys_hbm_rstgen/peripheral_aresetn] + +# clock gen connections + +ad_connect $sys_cpu_clk hbm_clk_wiz/clk_in1 # microblaze debug & interrupt