scripts: hp/mem updates
Rejeesh Kutty
parent
3211964c2e
commit
c1268f089d
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@ -65,37 +65,45 @@ proc ad_connect {p_name_1 p_name_2} {
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###################################################################################################
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###################################################################################################
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proc ad_mem_interconnect {p_clk p_name} {
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ad_mem_interconnect_int "MEM" $p_clk $p_name
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}
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proc ad_hp0_interconnect {p_clk p_name} {
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ad_mem_interconnect_int "HP0" $p_clk $p_name
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}
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proc ad_hp1_interconnect {p_clk p_name} {
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ad_mem_interconnect_int "HP1" $p_clk $p_name
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}
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proc ad_hp2_interconnect {p_clk p_name} {
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ad_mem_interconnect_int "HP2" $p_clk $p_name
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}
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proc ad_hp3_interconnect {p_name p_clk} {
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ad_mem_interconnect_int "HP3" $p_clk $p_name
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}
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###################################################################################################
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###################################################################################################
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proc ad_mem_interconnect_int {p_sel p_clk p_name} {
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proc ad_mem_hp0_interconnect {p_clk p_name} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
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}
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proc ad_mem_hp1_interconnect {p_clk p_name} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
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}
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proc ad_mem_hp2_interconnect {p_clk p_name} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
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}
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proc ad_mem_hp3_interconnect {p_name p_clk} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
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}
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###################################################################################################
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###################################################################################################
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proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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global sys_zynq
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global sys_ddr_addr_seg
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global sys_hp0_interconnect_index
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global sys_hp1_interconnect_index
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global sys_hp2_interconnect_index
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@ -107,34 +115,66 @@ proc ad_mem_interconnect_int {p_sel p_clk p_name} {
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set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_cell_name]] \
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-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
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if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
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if {$sys_hp0_interconnect_index == 0} {
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}
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if {$p_sel eq "MEM"} {
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set m_interconnect_index $sys_mem_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
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set m_addr_seg $sys_ddr_addr_seg
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}
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if {($p_sel eq "MEM") && ($sys_zynq == 1)} {
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set i_str "S$sys_mem_interconnect_index"
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if {$sys_mem_interconnect_index < 10} {
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set i_str "S0$sys_mem_interconnect_index"
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}
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if {$sys_mem_interconnect_index == -1} {
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ad_connect sys_cpu_resetn axi_mem_interconnect/ARESETN
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ad_connect $p_clk axi_mem_interconnect/ACLK
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ad_connect sys_cpu_resetn axi_mem_interconnect/M00_ARESETN
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ad_connect $p_clk axi_mem_interconnect/M00_ACLK
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ad_connect axi_mem_interconnect/M00_AXI $p_name
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} else {
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ad_connect sys_cpu_resetn axi_mem_interconnect/${i_str}_ARESETN
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ad_connect $p_clk axi_mem_interconnect/${i_str}_ACLK
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ad_connect axi_mem_interconnect/${i_str}_AXI $p_name
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ad_connect $p_clk $p_intf_clock
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}
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set sys_mem_interconnect_index [expr $sys_mem_interconnect_index + 1]
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if {$p_sel eq "HP0"} {
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set m_interconnect_index $sys_hp0_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
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}
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if {$p_sel eq "HP1"} {
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set m_interconnect_index $sys_hp1_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
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}
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if {$p_sel eq "HP2"} {
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set m_interconnect_index $sys_hp2_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
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}
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if {$p_sel eq "HP3"} {
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set m_interconnect_index $sys_hp3_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
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}
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set i_str "S$m_interconnect_index"
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if {$m_interconnect_index < 10} {
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set i_str "S0$m_interconnect_index"
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}
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set m_interconnect_index [expr $m_interconnect_index + 1]
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set_property CONFIG.NUM_MI 1 $m_interconnect_cell
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if {$m_interconnect_index == 0} {
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set_property CONFIG.NUM_SI 1 $m_interconnect_cell
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ad_connect sys_cpu_resetn $m_interconnect_cell/ARESETN
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ad_connect $p_clk $m_interconnect_cell/ACLK
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ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN
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ad_connect $p_clk $m_interconnect_cell/M00_ACLK
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ad_connect $m_interconnect_cell/M00_AXI $p_name
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ad_connect $p_clk $p_intf_clock
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} else {
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set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
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ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN
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ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
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ad_connect $m_interconnect_cell/${i_str}_AXI $p_name
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ad_connect $p_clk $p_intf_clock
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assign_bd_address $m_addr_seg
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}
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if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
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}
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###################################################################################################
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