adi_board: enable ps7 hp if needed
parent
59457cb3d4
commit
c0eef42647
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@ -126,15 +126,6 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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global sys_hp3_interconnect_index
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global sys_mem_interconnect_index
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set p_intf_name [lrange [split $p_name "/"] end end]
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set p_cell_name [lrange [split $p_name "/"] 0 0]
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set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
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CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
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CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
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if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
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set p_intf_clock ""
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}
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if {$p_sel eq "MEM"} {
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if {$sys_mem_interconnect_index < 0} {
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect
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@ -146,6 +137,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$p_sel eq "HP0"} {
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if {$sys_hp0_interconnect_index < 0} {
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set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp0_interconnect
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}
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set m_interconnect_index $sys_hp0_interconnect_index
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@ -155,6 +147,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$p_sel eq "HP1"} {
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if {$sys_hp1_interconnect_index < 0} {
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set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp1_interconnect
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}
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set m_interconnect_index $sys_hp1_interconnect_index
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@ -164,6 +157,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$p_sel eq "HP2"} {
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if {$sys_hp2_interconnect_index < 0} {
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set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp2_interconnect
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}
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set m_interconnect_index $sys_hp2_interconnect_index
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@ -173,6 +167,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$p_sel eq "HP3"} {
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if {$sys_hp3_interconnect_index < 0} {
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set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp3_interconnect
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}
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set m_interconnect_index $sys_hp3_interconnect_index
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@ -187,6 +182,15 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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set m_interconnect_index [expr $m_interconnect_index + 1]
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set p_intf_name [lrange [split $p_name "/"] end end]
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set p_cell_name [lrange [split $p_name "/"] 0 0]
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set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
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CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
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CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
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if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
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set p_intf_clock ""
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}
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if {$m_interconnect_index == 0} {
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set_property CONFIG.NUM_MI 1 $m_interconnect_cell
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set_property CONFIG.NUM_SI 1 $m_interconnect_cell
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