zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

adrv9379: Fix lane assignment, according to schematic

main
Adrian Costina 2018-03-05 15:13:13 +00:00 committed by István Csomortáni
parent 4bcf45a17a
commit c0184bce59
2 changed files with 5 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
projects/adrv9379/common/adrv9379_bd.tcl
View File

@ -137,7 +137,7 @@ ad_xcvrpll axi_ad9379_rx_os_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_3
ad_connect sys_cpu_resetn util_ad9379_xcvr/up_rstn
ad_connect sys_cpu_clk util_ad9379_xcvr/up_clk
ad_xcvrcon util_ad9379_xcvr axi_ad9379_tx_xcvr axi_ad9379_tx_jesd
ad_xcvrcon util_ad9379_xcvr axi_ad9379_tx_xcvr axi_ad9379_tx_jesd {0 3 2 1}
ad_reconct util_ad9379_xcvr/tx_out_clk_0 axi_ad9379_tx_clkgen/clk
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_0
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_1
@ -145,10 +145,6 @@ ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_2
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_3
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_tx_jesd/device_clk
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_tx_jesd_rstgen/slowest_sync_clk
ad_reconct util_ad9379_xcvr/tx_0 axi_ad9379_tx_jesd/tx_phy3
ad_reconct util_ad9379_xcvr/tx_1 axi_ad9379_tx_jesd/tx_phy0
ad_reconct util_ad9379_xcvr/tx_2 axi_ad9379_tx_jesd/tx_phy1
ad_reconct util_ad9379_xcvr/tx_3 axi_ad9379_tx_jesd/tx_phy2
ad_xcvrcon util_ad9379_xcvr axi_ad9379_rx_xcvr axi_ad9379_rx_jesd
ad_reconct util_ad9379_xcvr/rx_out_clk_0 axi_ad9379_rx_clkgen/clk
ad_connect axi_ad9379_rx_clkgen/clk_0 util_ad9379_xcvr/rx_clk_0

8
projects/adrv9379/zc706/system_constr.xdc
View File

@ -15,12 +15,12 @@ set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]]
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[0]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[0])
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[0]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[0])
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[1])
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[2]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[3])
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[3])
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[2]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[1])
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_p] ; ## G27 FMC_HPC_LA25_P (Sniffer)