From bfd84edc465c86753cdc3ccfde4265c8aac0f105 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 16 Apr 2015 11:26:09 +0200 Subject: [PATCH] adi_ip.tcl: adi_ip_constraints: Add support for VHDL projects Match both xilinx_verilogsynthesis and xilinx_vhdlsynthesis when getting the file group. Signed-off-by: Lars-Peter Clausen --- library/scripts/adi_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index 6870cd445..8d5216b20 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -47,7 +47,7 @@ proc adi_ip_files {ip_name ip_files} { proc adi_ip_constraints {ip_name ip_constr_files {processing_order early}} { - set proj_filegroup [ipx::get_file_groups xilinx_verilogsynthesis -of_objects [ipx::current_core]] + set proj_filegroup [ipx::get_file_groups xilinx_v*synthesis -of_objects [ipx::current_core]] set f [ipx::add_file $ip_constr_files $proj_filegroup] set_property -dict [list \ type xdc \