diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl
index 6081194a6..feb0e3ac8 100644
--- a/projects/common/kcu105/kcu105_system_bd.tcl
+++ b/projects/common/kcu105/kcu105_system_bd.tcl
@@ -33,7 +33,7 @@ set hdmi_data       [create_bd_port -dir O -from 15 -to 0 hdmi_data]
 set spdif           [create_bd_port -dir O spdif]
 
 set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
-set_property -dict [list CONFIG.FREQ_HZ {299000000}] $sys_clk
+set_property -dict [list CONFIG.FREQ_HZ {300000000}] $sys_clk
 set_property -dict [list CONFIG.FREQ_HZ {625000000}] $phy_clk
 
 # instance: microblaze - processor
@@ -170,7 +170,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
 # audio peripherals
 
 set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
-set_property -dict [list CONFIG.PRIM_IN_FREQ {199.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
 set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
 
 set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
diff --git a/projects/common/kcu105/kcu105_system_mig.tcl b/projects/common/kcu105/kcu105_system_mig.tcl
index bdf487394..fe09a9d47 100644
--- a/projects/common/kcu105/kcu105_system_mig.tcl
+++ b/projects/common/kcu105/kcu105_system_mig.tcl
@@ -1,18 +1,18 @@
 
-# ddr controller
+# ddr controller RevD
 
 set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM}] $axi_ddr_cntrl
-set_property -dict [list CONFIG.C0.DDR4_TimePeriod {1250}] $axi_ddr_cntrl
-set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3334}] $axi_ddr_cntrl
-set_property -dict [list CONFIG.C0.DDR4_MemoryPart {MT40A256M16HA-093}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3332}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.C0.DDR4_MemoryPart {EDY4016AABG-DR-F}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.C0.DDR4_DataWidth {64}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.C0.DDR4_Mem_Add_Map {ROW_BANK_COLUMN}] $axi_ddr_cntrl
-set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {9}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {12}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.Debug_Signal {Enable}] $axi_ddr_cntrl
 set_property -dict [list CONFIG.C0.DDR4_AxiDataWidth {512}] $axi_ddr_cntrl
 
-set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {99}] $axi_ddr_cntrl
-set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {199}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl
+set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl
 
 set_property -dict [list CONFIG.c0_adr_0               {bank45.byte3.pin8}]  $axi_ddr_cntrl  
 set_property -dict [list CONFIG.c0_adr_1               {bank45.byte2.pin1}]  $axi_ddr_cntrl