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ultrasound: disconnected ADN4670 chips from SPI lines. 

Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
main
Adrian Costina 2014-09-22 11:09:53 -04:00
parent 7e40f99fe9
commit bdf01738a1
3 changed files with 51 additions and 64 deletions
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10
projects/usdrx1/common/usdrx1_bd.tcl
View File

@ -1,8 +1,8 @@
# usdrx1
set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o]
set spi_csn_i [create_bd_port -dir I -from 4 -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 4 -to 0 spi_csn_o]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
@ -15,8 +15,6 @@ set rx_sysref [create_bd_port -dir O rx_sysref]
set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
#set mlo_clk [create_bd_port -dir O mlo_clk]
set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data]
set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0]
set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1]
@ -94,8 +92,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect
set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_SCK_RATIO {16}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi
# additions to default configuration

14
projects/usdrx1/common/usdrx1_spi.v
View File

@ -39,20 +39,17 @@
module usdrx1_spi (
spi_fout_csn,
spi_afe_csn,
spi_clk_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_fout_sdio,
spi_afe_sdio,
spi_clk_sdio);
// 4 wire
input [ 5:0] spi_fout_csn;
input [ 3:0] spi_afe_csn;
input spi_clk_csn;
input spi_clk;
@ -61,7 +58,6 @@ module usdrx1_spi (
// 3 wire
inout spi_fout_sdio;
inout spi_afe_sdio;
inout spi_clk_sdio;
@ -73,16 +69,14 @@ module usdrx1_spi (
// internal signals
wire [ 2:0] spi_csn_3_s;
wire [ 1:0] spi_csn_3_s;
wire spi_csn_s;
wire spi_enable_s;
wire spi_fout_miso_s;
wire spi_afe_miso_s;
wire spi_clk_miso_s;
// check on rising edge and change on falling edge
assign spi_csn_3_s[2] = & spi_fout_csn;
assign spi_csn_3_s[1] = & spi_afe_csn;
assign spi_csn_3_s[0] = spi_clk_csn;
assign spi_csn_s = & spi_csn_3_s;
@ -111,15 +105,11 @@ module usdrx1_spi (
end
end
assign spi_miso = ((spi_fout_miso_s & ~spi_csn_3_s[2]) |
(spi_afe_miso_s & ~spi_csn_3_s[1]) |
assign spi_miso = ((spi_afe_miso_s & ~spi_csn_3_s[1]) |
(spi_clk_miso_s & ~spi_csn_3_s[0]));
// io buffers
assign spi_fout_miso_s = spi_fout_sdio;
assign spi_fout_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
assign spi_afe_miso_s = spi_afe_sdio;
assign spi_afe_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;

21
projects/usdrx1/zc706/system_top.v
View File

@ -171,7 +171,7 @@ module system_top (
output spi_fout_enb_sysref;
output spi_fout_enb_trig;
output spi_fout_clk;
inout spi_fout_sdio;
output spi_fout_sdio;
output [ 3:0] spi_afe_csn;
output spi_afe_clk;
inout spi_afe_sdio;
@ -199,7 +199,7 @@ module system_top (
// internal signals
wire [10:0] spi_csn;
wire [ 4:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
@ -236,26 +236,25 @@ module system_top (
// spi assignments
assign spi_fout_enb_clk = ~spi_csn[10:10];
assign spi_fout_enb_mlo = ~spi_csn[ 9: 9];
assign spi_fout_enb_rst = ~spi_csn[ 8: 8];
assign spi_fout_enb_sync = ~spi_csn[ 7: 7];
assign spi_fout_enb_sysref = ~spi_csn[ 6: 6];
assign spi_fout_enb_trig = ~spi_csn[ 5: 5];
assign spi_fout_enb_clk = 1'b0;
assign spi_fout_enb_mlo = 1'b0;
assign spi_fout_enb_rst = 1'b0;
assign spi_fout_enb_sync = 1'b0;
assign spi_fout_enb_sysref = 1'b0;
assign spi_fout_enb_trig = 1'b0;
assign spi_fout_sdio = 1'b0;
assign spi_afe_csn = spi_csn[ 4: 1];
assign spi_clk_csn = spi_csn[ 0: 0];
assign spi_fout_clk = spi_clk;
assign spi_fout_clk = 1'b0;
assign spi_afe_clk = spi_clk;
assign spi_clk_clk = spi_clk;
usdrx1_spi i_spi (
.spi_fout_csn (spi_csn[10:5]),
.spi_afe_csn (spi_csn[4:1]),
.spi_clk_csn (spi_csn[0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_fout_sdio (spi_fout_sdio),
.spi_afe_sdio (spi_afe_sdio),
.spi_clk_sdio (spi_clk_sdio));