diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index edc9d01f6..ad8654d77 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -1,8 +1,8 @@ # usdrx1 -set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i] -set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o] +set spi_csn_i [create_bd_port -dir I -from 4 -to 0 spi_csn_i] +set spi_csn_o [create_bd_port -dir O -from 4 -to 0 spi_csn_o] set spi_clk_i [create_bd_port -dir I spi_clk_i] set spi_clk_o [create_bd_port -dir O spi_clk_o] set spi_sdo_i [create_bd_port -dir I spi_sdo_i] @@ -15,8 +15,6 @@ set rx_sysref [create_bd_port -dir O rx_sysref] set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] -#set mlo_clk [create_bd_port -dir O mlo_clk] - set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data] set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0] set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1] @@ -94,8 +92,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi] set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi -set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi -set_property -dict [list CONFIG.C_SCK_RATIO {16}] $axi_usdrx1_spi +set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi +set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi # additions to default configuration @@ -124,25 +122,25 @@ connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_u connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o] connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] -connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] +connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3] # connections (gt) -connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk] -connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] -connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] -connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] -connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref] +connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk] +connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] +connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] +connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] +connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref] # connections (adc) connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk_g] connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk] connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset] @@ -181,7 +179,7 @@ connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en] connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data] connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf] -connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] # interconnect (cpu) @@ -201,14 +199,14 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sy connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source @@ -217,14 +215,14 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESET connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] # interconnect (gt es) @@ -250,7 +248,7 @@ connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] -connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] +connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source @@ -259,7 +257,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk] connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source -connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] # ila diff --git a/projects/usdrx1/common/usdrx1_spi.v b/projects/usdrx1/common/usdrx1_spi.v index beed9891a..d4d3525f7 100644 --- a/projects/usdrx1/common/usdrx1_spi.v +++ b/projects/usdrx1/common/usdrx1_spi.v @@ -39,20 +39,17 @@ module usdrx1_spi ( - spi_fout_csn, spi_afe_csn, spi_clk_csn, spi_clk, spi_mosi, spi_miso, - spi_fout_sdio, spi_afe_sdio, spi_clk_sdio); // 4 wire - input [ 5:0] spi_fout_csn; input [ 3:0] spi_afe_csn; input spi_clk_csn; input spi_clk; @@ -61,7 +58,6 @@ module usdrx1_spi ( // 3 wire - inout spi_fout_sdio; inout spi_afe_sdio; inout spi_clk_sdio; @@ -73,16 +69,14 @@ module usdrx1_spi ( // internal signals - wire [ 2:0] spi_csn_3_s; + wire [ 1:0] spi_csn_3_s; wire spi_csn_s; wire spi_enable_s; - wire spi_fout_miso_s; wire spi_afe_miso_s; wire spi_clk_miso_s; // check on rising edge and change on falling edge - assign spi_csn_3_s[2] = & spi_fout_csn; assign spi_csn_3_s[1] = & spi_afe_csn; assign spi_csn_3_s[0] = spi_clk_csn; assign spi_csn_s = & spi_csn_3_s; @@ -111,15 +105,11 @@ module usdrx1_spi ( end end - assign spi_miso = ((spi_fout_miso_s & ~spi_csn_3_s[2]) | - (spi_afe_miso_s & ~spi_csn_3_s[1]) | + assign spi_miso = ((spi_afe_miso_s & ~spi_csn_3_s[1]) | (spi_clk_miso_s & ~spi_csn_3_s[0])); // io buffers - assign spi_fout_miso_s = spi_fout_sdio; - assign spi_fout_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; - assign spi_afe_miso_s = spi_afe_sdio; assign spi_afe_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index 410d3a0cd..758798222 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -171,7 +171,7 @@ module system_top ( output spi_fout_enb_sysref; output spi_fout_enb_trig; output spi_fout_clk; - inout spi_fout_sdio; + output spi_fout_sdio; output [ 3:0] spi_afe_csn; output spi_afe_clk; inout spi_afe_sdio; @@ -199,7 +199,7 @@ module system_top ( // internal signals - wire [10:0] spi_csn; + wire [ 4:0] spi_csn; wire spi_clk; wire spi_mosi; wire spi_miso; @@ -236,26 +236,25 @@ module system_top ( // spi assignments - assign spi_fout_enb_clk = ~spi_csn[10:10]; - assign spi_fout_enb_mlo = ~spi_csn[ 9: 9]; - assign spi_fout_enb_rst = ~spi_csn[ 8: 8]; - assign spi_fout_enb_sync = ~spi_csn[ 7: 7]; - assign spi_fout_enb_sysref = ~spi_csn[ 6: 6]; - assign spi_fout_enb_trig = ~spi_csn[ 5: 5]; + assign spi_fout_enb_clk = 1'b0; + assign spi_fout_enb_mlo = 1'b0; + assign spi_fout_enb_rst = 1'b0; + assign spi_fout_enb_sync = 1'b0; + assign spi_fout_enb_sysref = 1'b0; + assign spi_fout_enb_trig = 1'b0; + assign spi_fout_sdio = 1'b0; assign spi_afe_csn = spi_csn[ 4: 1]; assign spi_clk_csn = spi_csn[ 0: 0]; - assign spi_fout_clk = spi_clk; + assign spi_fout_clk = 1'b0; assign spi_afe_clk = spi_clk; assign spi_clk_clk = spi_clk; usdrx1_spi i_spi ( - .spi_fout_csn (spi_csn[10:5]), .spi_afe_csn (spi_csn[4:1]), .spi_clk_csn (spi_csn[0]), .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), - .spi_fout_sdio (spi_fout_sdio), .spi_afe_sdio (spi_afe_sdio), .spi_clk_sdio (spi_clk_sdio));