From bd6ec360e22d5ca116c061e056cb584fcec88f94 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 19 Apr 2021 14:57:19 +0100 Subject: [PATCH] ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs Organize XCVR params based on lane rate --- projects/ad9081_fmca_ebz/vcu118/system_bd.tcl | 56 ++++++++++++++++-- .../ad9081_fmca_ebz/vcu118/system_project.tcl | 34 ++++------- .../ad9081_fmca_ebz/vcu118/timing_constr.xdc | 58 +++++++++++++++++-- 3 files changed, 113 insertions(+), 35 deletions(-) diff --git a/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl b/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl index 722867f5b..5ea0329b1 100644 --- a/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl +++ b/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl @@ -20,7 +20,6 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file -if {$ad_project_params(JESD_MODE) == "8B10B"} { # Parameters for 15.5Gpbs lane rate ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31 @@ -47,6 +46,7 @@ ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00 ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3100 ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0 ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x54 ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1 ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c @@ -54,9 +54,53 @@ ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x2 ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20 ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xB00 ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2ff -} else { - set_property -dict [list CONFIG.ADDN_UI_CLKOUT4_FREQ_HZ {50}] [get_bd_cells axi_ddr_cntrl] - ad_connect /axi_ddr_cntrl/addn_ui_clkout4 jesd204_phy_121/drpclk - ad_connect /axi_ddr_cntrl/addn_ui_clkout4 jesd204_phy_126/drpclk -} +# 204C params 16.5Gbps..24.75Gpbs +if {$ad_project_params(JESD_MODE) == "64B66B"} { + # Lane rate indepentent parameters + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0 + ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x2 + ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6060 + ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 2 + ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 2 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG2 0x281C + ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG3 0x4120 + + # set dividers for 24.75Gbps, are overwritten by software + ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 10 + ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 10 + ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 66 + ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 2 + + if {$ad_project_params(RX_LANE_RATE) < 20} { + ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x0104 + } else { + ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x6 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3004 + } + + if {$ad_project_params(TX_LANE_RATE) < 20} { + ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C2 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x0100 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x1000 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 0 + } else { + ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 3 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C6 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xF800 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xF800 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xF800 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3000 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0 + ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 1 + } + +} diff --git a/projects/ad9081_fmca_ebz/vcu118/system_project.tcl b/projects/ad9081_fmca_ebz/vcu118/system_project.tcl index 473f388eb..bac1e1485 100644 --- a/projects/ad9081_fmca_ebz/vcu118/system_project.tcl +++ b/projects/ad9081_fmca_ebz/vcu118/system_project.tcl @@ -9,29 +9,17 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Use over-writable parameters from the environment. # # e.g. -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 REF_CLK_RATE=250 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 RX_PLL_SEL=2 TX_PLL_SEL=2 -# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 REF_CLK_RATE=375 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 -# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 REF_CLK_RATE=250 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 RX_PLL_SEL=2 TX_PLL_SEL=2 +# make JESD_MODE=64B66B RX_JESD_L=4 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 +# make JESD_MODE=64B66B RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 # make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 -# RX_RATE,TX_RATE,REF_CLK_RATE used only in 64B66B mode - # # Parameter description: # JESD_MODE : Used link layer encoder mode -# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer -# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer -# -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode -# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode -# Encoding is: -# 0 - CPLL -# 1 - QPLL0 -# 2 - QPLL1 -# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode +# 64B66B - 64b66b link layer defined in JESD 204C +# 8B10B - 8b10b link layer defined in JESD 204B # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_NP : Number of bits per sample @@ -40,11 +28,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project ad9081_fmca_ebz_vcu118 0 [list \ JESD_MODE [get_env_param JESD_MODE 8B10B ] \ - RX_RATE [get_env_param RX_RATE 10 ] \ - RX_PLL_SEL [get_env_param RX_PLL_SEL 1 ] \ - TX_RATE [get_env_param TX_RATE 10 ] \ - TX_PLL_SEL [get_env_param TX_PLL_SEL 1 ] \ - REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \ RX_JESD_M [get_env_param RX_JESD_M 8 ] \ RX_JESD_L [get_env_param RX_JESD_L 4 ] \ RX_JESD_S [get_env_param RX_JESD_S 1 ] \ @@ -67,6 +50,11 @@ adi_project_files ad9081_fmca_ebz_vcu118 [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ] +# Avoid critical warning in OOC mode from the clock definitions +# since at that stage the submodules are not stiched together yet +if {$ADI_USE_OOC_SYNTHESIS == 1} { + set_property used_in_synthesis false [get_files timing_constr.xdc] +} adi_project_run ad9081_fmca_ebz_vcu118 diff --git a/projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc b/projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc index 79a643a85..a8efd11d4 100644 --- a/projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc +++ b/projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc @@ -1,20 +1,66 @@ # Primary clock definitions +# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block +# Maximum values for Link clock: +# 204B - 15.5 Gbps /40 = 387.5MHz +# 204C - 24.75 Gbps /66 = 375MHz + +set link_mode [get_property LINK_MODE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]] + +set rx_lane_rate [get_property RX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]] +set tx_lane_rate [get_property TX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]] + +set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] +set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] + +set rx_link_clk_period [expr 1000/$rx_link_clk] +set tx_link_clk_period [expr 1000/$tx_link_clk] + +set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]] +set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]] +set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]] +set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]] + +set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width] +set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] +set rx_device_clk_period [expr 1000/$rx_device_clk] +set tx_device_clk_period [expr 1000/$tx_device_clk] + # refclk and refclk_replica are connect to the same source on the PCB -create_clock -name refclk -period 4 [get_ports fpga_refclk_in_p] -create_clock -name refclk_replica -period 4 [get_ports fpga_refclk_in_replica_p] +# Set reference clock to same frequency as the link clock, +# this will ease the XCVR out clocks propagation calculation. +# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE +create_clock -name refclk -period $rx_link_clk_period [get_ports fpga_refclk_in_p] +create_clock -name refclk_replica -period $rx_link_clk_period [get_ports fpga_refclk_in_replica_p] # device clock -create_clock -name tx_device_clk -period 4 [get_ports clkin6_p] -create_clock -name rx_device_clk -period 4 [get_ports clkin8_p] - +create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clkin8_p] +create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports clkin6_p] # Constraint SYSREFs # Assumption is that REFCLK and SYSREF have similar propagation delay, # and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK -set_input_delay -clock [get_clocks tx_device_clk] \ +set_input_delay -clock [get_clocks rx_device_clk] \ + [get_property PERIOD [get_clocks rx_device_clk]] \ + [get_ports {sysref2_*}] +set_input_delay -clock [get_clocks tx_device_clk] -add_delay\ [get_property PERIOD [get_clocks tx_device_clk]] \ [get_ports {sysref2_*}] +set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous +# For transceiver output clocks use reference clock divided by one +# This will help autoderive the clocks correcly +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]] + +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]] +