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Remove unused DMA overflow signal from DAC DMA interfaces 

The DAC DMA will never overflow and unsurprisingly the dac_dovf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-05-05 19:05:49 +02:00 committed by Lars-Peter Clausen
parent f647dd4c0a
commit bd251a5fd5
31 changed files with 2 additions and 61 deletions
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1
library/axi_ad5766/axi_ad5766.v
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@ -361,7 +361,6 @@ module axi_ad5766 #(
.dac_datafmt (dac_datafmt),
.dac_datarate (dac_datarate_s),
.dac_status (1'b0),
.dac_status_ovf (1'b0),
.dac_status_unf (dma_underflow),
.dac_clk_ratio (32'b0),
.up_dac_ce (),

2
library/axi_ad9122/axi_ad9122.v
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@ -74,7 +74,6 @@ module axi_ad9122 #(
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// axi interface
@ -230,7 +229,6 @@ module axi_ad9122 #(
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.mmcm_rst (mmcm_rst),
.up_drp_sel (up_drp_sel_s),

2
library/axi_ad9122/axi_ad9122_core.v
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@ -75,7 +75,6 @@ module axi_ad9122_core #(
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// mmcm reset
@ -221,7 +220,6 @@ module axi_ad9122_core #(
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (dac_status),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.up_dac_ce (),

1
library/axi_ad9122/axi_ad9122_hw.tcl
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@ -84,7 +84,6 @@ add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_dac_div_clk
set_interface_property dac_ch_1 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf
# SERDES instances and configurations

1
library/axi_ad9122/axi_ad9122_ip.tcl
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@ -33,7 +33,6 @@ adi_ip_properties axi_ad9122
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface dac_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

2
library/axi_ad9144/axi_ad9144.v
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@ -64,7 +64,6 @@ module axi_ad9144 #(
output dac_valid_3,
output dac_enable_3,
input [63:0] dac_ddata_3,
input dac_dovf,
input dac_dunf,
// axi interface
@ -193,7 +192,6 @@ module axi_ad9144 #(
.dac_valid_3 (dac_valid_3),
.dac_enable_3 (dac_enable_3),
.dac_ddata_3 (dac_ddata_3),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),

2
library/axi_ad9144/axi_ad9144_core.v
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@ -75,7 +75,6 @@ module axi_ad9144_core #(
output dac_valid_3,
output dac_enable_3,
input [63:0] dac_ddata_3,
input dac_dovf,
input dac_dunf,
// processor interface
@ -234,7 +233,6 @@ module axi_ad9144_core #(
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.up_dac_ce (),

1
library/axi_ad9144/axi_ad9144_hw.tcl
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@ -80,7 +80,6 @@ for {set i 0} {$i < 4} {incr i} {
set_interface_property dac_ch_${i} associatedReset none
}
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf
proc p_axi_ad9144 {} {

1
library/axi_ad9144/axi_ad9144_ip.tcl
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@ -27,7 +27,6 @@ adi_ip_files axi_ad9144 [list \
adi_ip_properties axi_ad9144
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]

2
library/axi_ad9152/axi_ad9152.v
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@ -57,7 +57,6 @@ module axi_ad9152 #(
output dac_valid_1,
output dac_enable_1,
input [ 63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// axi interface
@ -151,7 +150,6 @@ module axi_ad9152 #(
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),

2
library/axi_ad9152/axi_ad9152_core.v
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@ -61,7 +61,6 @@ module axi_ad9152_core #(
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// processor interface
@ -180,7 +179,6 @@ module axi_ad9152_core #(
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.up_dac_ce (),

1
library/axi_ad9152/axi_ad9152_hw.tcl
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@ -78,6 +78,5 @@ add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_tx_clk
set_interface_property dac_ch_1 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf

1
library/axi_ad9152/axi_ad9152_ip.tcl
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@ -27,7 +27,6 @@ adi_ip_files axi_ad9152 [list \
adi_ip_properties axi_ad9152
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]

2
library/axi_ad9162/axi_ad9162.v
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@ -54,7 +54,6 @@ module axi_ad9162 #(
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// axi interface
@ -129,7 +128,6 @@ module axi_ad9162 #(
.dac_valid (dac_valid),
.dac_enable (dac_enable),
.dac_ddata (dac_ddata),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),

2
library/axi_ad9162/axi_ad9162_core.v
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@ -51,7 +51,6 @@ module axi_ad9162_core #(
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// processor interface
@ -143,7 +142,6 @@ module axi_ad9162_core #(
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd16),
.up_dac_ce (),

1
library/axi_ad9162/axi_ad9162_ip.tcl
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@ -27,7 +27,6 @@ adi_ip_files axi_ad9162 [list \
adi_ip_properties axi_ad9162
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]

2
library/axi_ad9361/axi_ad9361.v
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@ -148,7 +148,6 @@ module axi_ad9361 #(
output dac_enable_q1,
output dac_valid_q1,
input [15:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
output dac_r1_mode,
@ -667,7 +666,6 @@ module axi_ad9361 #(
.dac_enable_q1 (dac_enable_q1),
.dac_valid_q1 (dac_valid_q1_s),
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_pps_rcounter (up_pps_rcounter_s),
.up_pps_status (up_pps_status_s),

1
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -149,7 +149,6 @@ add_interface_port dac_ch_3 dac_data_q1 data Input 16
set_interface_property dac_ch_3 associatedClock if_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf
ad_alt_intf signal dac_r1_mode output 1 r1_mode

2
library/axi_ad9361/axi_ad9361_tx.v
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@ -87,7 +87,6 @@ module axi_ad9361_tx #(
output dac_enable_q1,
output dac_valid_q1,
input [15:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// gpio
@ -358,7 +357,6 @@ module axi_ad9361_tx #(
.dac_datafmt (dac_dds_format_s),
.dac_datarate (dac_datarate_s),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd1),
.up_dac_ce (),

2
library/axi_ad9371/axi_ad9371.v
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@ -104,7 +104,6 @@ module axi_ad9371 #(
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// axi interface
@ -285,7 +284,6 @@ module axi_ad9371 #(
.dac_enable_q1 (dac_enable_q1),
.dac_valid_q1 (dac_valid_q1),
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),

1
library/axi_ad9371/axi_ad9371_hw.tcl
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@ -195,6 +195,5 @@ add_interface_port dac_ch_3 dac_data_q1 data Input 32
set_interface_property dac_ch_3 associatedClock if_dac_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf

2
library/axi_ad9371/axi_ad9371_tx.v
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@ -65,7 +65,6 @@ module axi_ad9371_tx #(
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// processor interface
@ -254,7 +253,6 @@ module axi_ad9371_tx #(
.dac_datafmt (dac_dds_format_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd2),
.up_dac_ce (),

2
library/axi_ad9739a/axi_ad9739a.v
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@ -61,7 +61,6 @@ module axi_ad9739a #(
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// axi interface
@ -185,7 +184,6 @@ module axi_ad9739a #(
.dac_valid (dac_valid),
.dac_enable (dac_enable),
.dac_ddata (dac_ddata),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),

2
library/axi_ad9739a/axi_ad9739a_core.v
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@ -67,7 +67,6 @@ module axi_ad9739a_core #(
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// processor interface
@ -169,7 +168,6 @@ module axi_ad9739a_core #(
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (dac_status),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd16),
.up_dac_ce (),

1
library/axi_ad9739a/axi_ad9739a_ip.tcl
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@ -28,7 +28,6 @@ adi_ip_files axi_ad9739a [list \
adi_ip_properties axi_ad9739a
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

2
library/axi_ad9963/axi_ad9963.v
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@ -96,7 +96,6 @@ module axi_ad9963 #(
output dac_enable_q,
output dac_valid_q,
input [15:0] dac_data_q,
input dac_dovf,
input dac_dunf,
// axi interface
@ -266,7 +265,6 @@ module axi_ad9963 #(
.dac_enable_q (dac_enable_q),
.dac_valid_q (dac_valid_q),
.dac_data_q (dac_data_q),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_dac_ce(up_dac_ce),
.up_rstn (up_rstn),

2
library/axi_ad9963/axi_ad9963_tx.v
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@ -63,7 +63,6 @@ module axi_ad9963_tx #(
output dac_enable_q,
output reg dac_valid_q,
input [15:0] dac_data_q,
input dac_dovf,
input dac_dunf,
output up_dac_ce,
@ -197,7 +196,6 @@ module axi_ad9963_tx #(
.dac_datafmt (dac_dds_format_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd1),
.up_dac_ce(up_dac_ce),

2
library/axi_adrv9009/axi_adrv9009.v
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@ -104,7 +104,6 @@ module axi_adrv9009 #(
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// axi interface
@ -285,7 +284,6 @@ module axi_adrv9009 #(
.dac_enable_q1 (dac_enable_q1),
.dac_valid_q1 (dac_valid_q1),
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),

1
library/axi_adrv9009/axi_adrv9009_hw.tcl
View File

@ -195,6 +195,5 @@ add_interface_port dac_ch_3 dac_data_q1 data Input 32
set_interface_property dac_ch_3 associatedClock if_dac_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf

2
library/axi_adrv9009/axi_adrv9009_tx.v
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@ -65,7 +65,6 @@ module axi_adrv9009_tx #(
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// processor interface
@ -262,7 +261,6 @@ module axi_adrv9009_tx #(
.dac_datafmt (dac_dds_format_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd2),
.up_dac_ce (),

15
library/common/up_dac_common.v
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@ -64,7 +64,6 @@ module up_dac_common #(
output dac_datafmt,
output [15:0] dac_datarate,
input dac_status,
input dac_status_ovf,
input dac_status_unf,
input [31:0] dac_clk_ratio,
output up_dac_ce,
@ -124,7 +123,6 @@ module up_dac_common #(
reg [15:0] up_dac_datarate = 'd0;
reg up_dac_frame = 'd0;
reg up_dac_clksel = CLK_EDGE_SEL;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax_int = 'd0;
reg [31:0] up_dac_gpio_out_int = 'd0;
@ -145,7 +143,6 @@ module up_dac_common #(
wire up_rreq_s;
wire up_xfer_done_s;
wire up_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire dac_sync_s;
wire dac_frame_s;
@ -298,14 +295,8 @@ module up_dac_common #(
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
end else begin
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[1];
end
if (up_status_unf_s == 1'b1) begin
up_status_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
@ -399,7 +390,7 @@ module up_dac_common #(
8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
8'h1e: up_rdata_int <= up_drp_wdata;
8'h1f: up_rdata_int <= up_drp_rdata_hold_s;
8'h22: up_rdata_int <= {30'd0, up_status_ovf, up_status_unf};
8'h22: up_rdata_int <= {31'd0, up_status_unf};
8'h28: up_rdata_int <= {24'd0, dac_usr_chanmax};
8'h2e: up_rdata_int <= up_dac_gpio_in;
8'h2f: up_rdata_int <= up_dac_gpio_out_int;
@ -444,16 +435,14 @@ module up_dac_common #(
dac_datafmt,
dac_datarate}));
up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_status_s,
up_status_ovf_s,
up_status_unf_s}),
.d_rst (dac_rst),
.d_clk (dac_clk),
.d_data_status ({ dac_status,
dac_status_ovf,
dac_status_unf}));
// generate frame and enable