diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile new file mode 100644 index 000000000..f6284afab --- /dev/null +++ b/projects/pzsdr1/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +.PHONY: all clean clean-all +all: + -make -C ccbrk all + -make -C ccfmc all + -make -C ccpci all + + +clean: + make -C ccbrk clean + make -C ccfmc clean + make -C ccpci clean + + +clean-all: + make -C ccbrk clean-all + make -C ccfmc clean-all + make -C ccpci clean-all + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr1/ccbrk/Makefile b/projects/pzsdr1/ccbrk/Makefile new file mode 100644 index 000000000..49d742665 --- /dev/null +++ b/projects/pzsdr1/ccbrk/Makefile @@ -0,0 +1,84 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/ccbrk_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl +M_DEPS += ../../common/xilinx/sys_wfifo.tcl +M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl +M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc +M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr +M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += .Xil + + + +.PHONY: all lib clean clean-all +all: lib ccbrk_pzsdr.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_gpreg clean + make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_gtlb clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS) + rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_gpreg + make -C ../../../library/axi_jesd_gt + make -C ../../../library/util_cpack + make -C ../../../library/util_gtlb + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr1/ccbrk/system_bd.tcl b/projects/pzsdr1/ccbrk/system_bd.tcl new file mode 100644 index 000000000..4907eef1b --- /dev/null +++ b/projects/pzsdr1/ccbrk/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl +source ../common/ccbrk_bd.tcl + diff --git a/projects/pzsdr1/ccbrk/system_constr.xdc b/projects/pzsdr1/ccbrk/system_constr.xdc new file mode 100644 index 000000000..05083fdc9 --- /dev/null +++ b/projects/pzsdr1/ccbrk/system_constr.xdc @@ -0,0 +1,258 @@ + +## constraints +## loopback +## p4 + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## IO_L2P_T0_33 +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_in[0]] ; ## IO_L1P_T0_33 +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports gp_out[1]] ; ## IO_L2N_T0_33 +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_in[1]] ; ## IO_L1N_T0_33 +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports gp_out[2]] ; ## IO_L4P_T0_33 +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports gp_in[2]] ; ## IO_L3P_T0_DQS_33 +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18} [get_ports gp_out[3]] ; ## IO_L4N_T0_33 +set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports gp_in[3]] ; ## IO_L3N_T0_DQS_33 +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18} [get_ports gp_out[4]] ; ## IO_L6P_T0_33 +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports gp_in[4]] ; ## IO_L5P_T0_33 +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports gp_out[5]] ; ## IO_L6N_T0_VREF_33 +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports gp_in[5]] ; ## IO_L5N_T0_33 +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports gp_out[6]] ; ## IO_L8P_T1_33 +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports gp_in[6]] ; ## IO_L7P_T1_33 +set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports gp_out[7]] ; ## IO_L8N_T1_33 +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18} [get_ports gp_in[7]] ; ## IO_L7N_T1_33 +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18} [get_ports gp_out[8]] ; ## IO_L10P_T1_33 +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports gp_in[8]] ; ## IO_L9P_T1_DQS_33 +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18} [get_ports gp_out[9]] ; ## IO_L10N_T1_33 +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports gp_in[9]] ; ## IO_L9N_T1_DQS_33 +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_out[10]] ; ## IO_L12P_T1_MRCC_33 +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports gp_in[10]] ; ## IO_L11P_T1_SRCC_33 + +## p5 + +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_out[11]] ; ## IO_L17P_T2_33 +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_in[11]] ; ## IO_L16P_T2_33 +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_out[12]] ; ## IO_L17N_T2_33 +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_in[12]] ; ## IO_L16N_T2_33 +set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_out[13]] ; ## IO_L19P_T3_33 +set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_in[13]] ; ## IO_L18P_T2_33 +set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_out[14]] ; ## IO_L19N_T3_VREF_33 +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_in[14]] ; ## IO_L18N_T2_33 +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_out[15]] ; ## IO_L20P_T3_33 +set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_in[15]] ; ## IO_L21P_T3_DQS_33 +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_out[16]] ; ## IO_L20N_T3_33 +set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_in[16]] ; ## IO_L21N_T3_DQS_33 +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_out[17]] ; ## IO_L22P_T3_33 +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[17]] ; ## IO_L23P_T3_33 +set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_out[18]] ; ## IO_L22N_T3_33 +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[18]] ; ## IO_L23N_T3_33 +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gp_out[19]] ; ## IO_25_VRP_34 +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports gp_in[19]] ; ## IO_L10N_T1_34 +set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_out[20]] ; ## IO_L14P_T2_SRCC_33 +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_in[20]] ; ## IO_L24P_T3_33 +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_out[21]] ; ## IO_L14N_T2_SRCC_33 +set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_in[21]] ; ## IO_L24N_T3_33 +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## IO_L13P_T2_MRCC_33 +set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## IO_L15P_T2_DQS_33 +set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## IO_L13N_T2_MRCC_33 +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_in[23]] ; ## IO_L15N_T2_DQS_33 + +## p6 + +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_out[24]] ; ## IO_L2P_T0_34 +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[24]] ; ## IO_L1P_T0_34 +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_out[25]] ; ## IO_L2N_T0_34 +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[25]] ; ## IO_L1N_T0_34 +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_out[26]] ; ## IO_L4P_T0_34 +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_in[26]] ; ## IO_L3P_T0_DQS_PUDC_B_34 +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_out[27]] ; ## IO_L4N_T0_34 +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_in[27]] ; ## IO_L3N_T0_DQS_34 +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports gp_out[28]] ; ## IO_L6P_T0_34 +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_in[28]] ; ## IO_L5P_T0_34 +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports gp_out[29]] ; ## IO_L6N_T0_VREF_34 +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gp_in[29]] ; ## IO_L5N_T0_34 +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports gp_out[30]] ; ## IO_L8P_T1_34 +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports gp_in[30]] ; ## IO_L7P_T1_34 +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports gp_out[31]] ; ## IO_L12P_T1_MRCC_34 +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports gp_in[31]] ; ## IO_L11P_T1_SRCC_34 +set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports gp_out[32]] ; ## IO_L12N_T1_MRCC_34 +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports gp_in[32]] ; ## IO_L11N_T1_SRCC_34 + +## p7 + +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports gp_out[33]] ; ## IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports gp_in[33]] ; ## IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports gp_out[34]] ; ## IO_L14N_T2_SRCC_34 +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports gp_in[34]] ; ## IO_L13N_T2_MRCC_34 +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports gp_out[35]] ; ## IO_L16P_T2_34 +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports gp_in[35]] ; ## IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports gp_out[36]] ; ## IO_L16N_T2_34 +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports gp_in[36]] ; ## IO_L15N_T2_DQS_34 +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L19P_T3_34 +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## IO_L20N_T3_34 +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L19N_T3_VREF_34 +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## IO_L22P_T3_34 +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## IO_L21P_T3_DQS_34 +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## IO_L22N_T3_34 +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## IO_L21N_T3_DQS_34 +set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## IO_0_VRN_33 +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## IO_L18P_T2_34 +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## IO_L18N_T2_34 +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## IO_25_VRP_33 + +## p13 + +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_out[43]] ; ## IO_L16P_T2_12 +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_in[43]] ; ## IO_L15P_T2_DQS_12 +set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_out[44]] ; ## IO_L16N_T2_12 +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_in[44]] ; ## IO_L15N_T2_DQS_12 +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_out[45]] ; ## IO_L14P_T2_SRCC_12 +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports gp_in[45]] ; ## IO_L13P_T2_MRCC_12 +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_out[46]] ; ## IO_L14N_T2_SRCC_12 +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gp_in[46]] ; ## IO_L13N_T2_MRCC_12 +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_out[47]] ; ## IO_L12P_T1_MRCC_12 +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_in[47]] ; ## IO_L11P_T1_SRCC_12 +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_out[48]] ; ## IO_L12N_T1_MRCC_12 +set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_in[48]] ; ## IO_L11N_T1_SRCC_12 +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_out[49]] ; ## IO_L10P_T1_12 +set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_in[49]] ; ## IO_L9P_T1_DQS_12 +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_out[50]] ; ## IO_L10N_T1_12 +set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_in[50]] ; ## IO_L9N_T1_DQS_12 +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_out[51]] ; ## IO_L8P_T1_12 +set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_in[51]] ; ## IO_L7P_T1_12 +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_out[52]] ; ## IO_L8N_T1_12 +set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_in[52]] ; ## IO_L7N_T1_12 +set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_out[53]] ; ## IO_L6P_T0_12 +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_in[53]] ; ## IO_L5P_T0_12 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_out[54]] ; ## IO_L6N_T0_VREF_12 +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_in[54]] ; ## IO_L5N_T0_12 +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_out[55]] ; ## IO_L4P_T0_12 +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_in[55]] ; ## IO_L3P_T0_DQS_12 +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_out[56]] ; ## IO_L4N_T0_12 +set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_in[56]] ; ## IO_L3N_T0_DQS_12 +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_out[57]] ; ## IO_L2P_T0_12 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_in[57]] ; ## IO_L1P_T0_12 +set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_out[58]] ; ## IO_L2N_T0_12 +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_in[58]] ; ## IO_L1N_T0_12 +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_out[59]] ; ## IO_L18P_T2_12 +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_in[59]] ; ## IO_L17P_T2_12 +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_out[60]] ; ## IO_L18N_T2_12 +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_in[60]] ; ## IO_L17N_T2_12 +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_out[61]] ; ## IO_L20P_T3_12 +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_in[61]] ; ## IO_L19P_T3_12 +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_out[62]] ; ## IO_L20N_T3_12 +set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_in[62]] ; ## IO_L19N_T3_VREF_12 +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_out[63]] ; ## IO_L22P_T3_12 +set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_in[63]] ; ## IO_L21P_T3_DQS_12 +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gp_out[64]] ; ## IO_L22N_T3_12 +set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_in[64]] ; ## IO_L21N_T3_DQS_12 + +## p2 + +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_out[65]] ; ## IO_25_13 +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gp_in[65]] ; ## IO_L6P_T0_13 +set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_out[66]] ; ## IO_L2P_T0_13 +set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_in[66]] ; ## IO_L1P_T0_13 +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_out[67]] ; ## IO_L2N_T0_13 +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_in[67]] ; ## IO_L1N_T0_13 +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_out[68]] ; ## IO_L4P_T0_13 +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_in[68]] ; ## IO_L3P_T0_DQS_13 +set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_out[69]] ; ## IO_L4N_T0_13 +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_in[69]] ; ## IO_L3N_T0_DQS_13 +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_out[70]] ; ## IO_L8P_T1_13 +set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_in[70]] ; ## IO_L7P_T1_13 +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_out[71]] ; ## IO_L8N_T1_13 +set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_in[71]] ; ## IO_L7N_T1_13 +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_out[72]] ; ## IO_L10P_T1_13 +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_in[72]] ; ## IO_L9P_T1_DQS_13 +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_out[73]] ; ## IO_L10N_T1_13 +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_in[73]] ; ## IO_L9N_T1_DQS_13 +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_out[74]] ; ## IO_L12P_T1_MRCC_13 +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_in[74]] ; ## IO_L11P_T1_SRCC_13 +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_out[75]] ; ## IO_L12N_T1_MRCC_13 +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_in[75]] ; ## IO_L11N_T1_SRCC_13 +set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_out[76]] ; ## IO_L14P_T2_SRCC_13 +set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS25} [get_ports gp_in[76]] ; ## IO_L13P_T2_MRCC_13 +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_out[77]] ; ## IO_L14N_T2_SRCC_13 +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports gp_in[77]] ; ## IO_L13N_T2_MRCC_13 +set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_out[78]] ; ## IO_L16P_T2_13 +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_in[78]] ; ## IO_L15P_T2_DQS_13 +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_out[79]] ; ## IO_L16N_T2_13 +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_in[79]] ; ## IO_L15N_T2_DQS_13 +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_out[80]] ; ## IO_L18P_T2_13 +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_in[80]] ; ## IO_L17P_T2_13 +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_out[81]] ; ## IO_L18N_T2_13 +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_in[81]] ; ## IO_L17N_T2_13 +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gp_out[82]] ; ## IO_L20P_T3_13 +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[82]] ; ## IO_L19P_T3_13 +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gp_out[83]] ; ## IO_L20N_T3_13 +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[83]] ; ## IO_L19N_T3_VREF_13 +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[84]] ; ## IO_L22P_T3_13 +set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_in[84]] ; ## IO_L21P_T3_DQS_13 +set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[85]] ; ## IO_L22N_T3_13 +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_in[85]] ; ## IO_L21N_T3_DQS_13 +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_out[86]] ; ## IO_L24P_T3_13 +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[86]] ; ## IO_L23P_T3_13 +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_out[87]] ; ## IO_L24N_T3_13 +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_in[87]] ; ## IO_L23N_T3_13 + +## vcc + +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gp_in_1] ; ## IO_L6N_T0_VREF_13 + +## on board + +set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_p] ; ## MGTREFCLK0P_111 +set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_n] ; ## MGTREFCLK0N_111 +set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_p[0]] ; ## MGTXRXP0_111 +set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_n[0]] ; ## MGTXRXN0_111 +set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## MGTXRXP1_111 +set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## MGTXRXN1_111 +set_property -dict {PACKAGE_PIN AC6} [get_ports gt_rx_p[2]] ; ## MGTXRXP2_111 +set_property -dict {PACKAGE_PIN AC5} [get_ports gt_rx_n[2]] ; ## MGTXRXN2_111 +set_property -dict {PACKAGE_PIN AD4} [get_ports gt_rx_p[3]] ; ## MGTXRXP3_111 +set_property -dict {PACKAGE_PIN AD3} [get_ports gt_rx_n[3]] ; ## MGTXRXN3_111 +set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_p[0]] ; ## MGTXTXP0_111 +set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_n[0]] ; ## MGTXTXN0_111 +set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## MGTXTXP1_111 +set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## MGTXTXN1_111 +set_property -dict {PACKAGE_PIN AE2} [get_ports gt_tx_p[2]] ; ## MGTXTXP2_111 +set_property -dict {PACKAGE_PIN AE1} [get_ports gt_tx_n[2]] ; ## MGTXTXN2_111 +set_property -dict {PACKAGE_PIN AC2} [get_ports gt_tx_p[3]] ; ## MGTXTXP3_111 +set_property -dict {PACKAGE_PIN AC1} [get_ports gt_tx_n[3]] ; ## MGTXTXN3_111 + +## clocks + +create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p] +create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] + +## MIO loopbacks (fixed-io) +## the following are connected to AD9361 GPIO + +## JX4.86 A23 PS_MIO12_500_JX4 <==> JX4.2 NA AD9361_GPO1 +## JX4.88 B26 PS_MIO11_500_JX4 <==> JX4.1 NA AD9361_GPO0 +## JX4.91 B25 PS_MIO13_500_JX4 <==> JX4.3 NA AD9361_GPO2 +## JX4.93 D23 PS_MIO14_500_JX4 <==> JX4.4 NA AD9361_GPO3 + +## the following are mio-to-mio loopback (excluding Push-Buttons to LED) + +## JX4.92 E17 PS_MIO46_501_JX4 <==> JX4.94 B19 PS_MIO47_501_JX4 + +## the following are mio-to-pl loopback + +## JX4.97 E26 PS_MIO00_500_JX4 <==> JX1.76 K3 IO_L11N_T1_SRCC_33 +## JX4.100 B20 PS_MIO51_501_JX4 <==> JX4.67 A9 IO_L17P_T2_34 +## JX4.85 C24 PS_MIO15_500_JX4 <==> JX4.37 E5 IO_L7N_T1_34 +## JX4.87 A25 PS_MIO10_500_JX4 <==> JX4.42 E6 IO_L10P_T1_34 + +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[0]] ; ## IO_L11N_T1_SRCC_33 +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[1]] ; ## IO_L17P_T2_34 +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[2]] ; ## IO_L7N_T1_34 +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[3]] ; ## IO_L10P_T1_34 + diff --git a/projects/pzsdr1/ccbrk/system_project.tcl b/projects/pzsdr1/ccbrk/system_project.tcl new file mode 100644 index 000000000..3d182ce37 --- /dev/null +++ b/projects/pzsdr1/ccbrk/system_project.tcl @@ -0,0 +1,20 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create ccbrk_pzsdr +adi_project_files ccbrk_pzsdr [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ] + +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + +adi_project_run ccbrk_pzsdr + + diff --git a/projects/pzsdr1/ccbrk/system_top.v b/projects/pzsdr1/ccbrk/system_top.v new file mode 100644 index 000000000..585b2022d --- /dev/null +++ b/projects/pzsdr1/ccbrk/system_top.v @@ -0,0 +1,331 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + iic_scl, + iic_sda, + + gpio_bd, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + enable, + txnrx, + clk_out, + + gpio_clksel, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + gp_out, + gp_in, + gp_in_mio, + gp_in_1, + + gt_ref_clk_p, + gt_ref_clk_n, + gt_tx_p, + gt_tx_n, + gt_rx_p, + gt_rx_n); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout iic_scl; + inout iic_sda; + + inout [11:0] gpio_bd; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + output enable; + output txnrx; + input clk_out; + + inout gpio_clksel; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + output [87:0] gp_out; + input [87:0] gp_in; + input [ 3:0] gp_in_mio; + input gp_in_1; + + input gt_ref_clk_p; + input gt_ref_clk_n; + output [ 3:0] gt_tx_p; + output [ 3:0] gt_tx_n; + input [ 3:0] gt_rx_p; + input [ 3:0] gt_rx_n; + + // internal signals + + wire gt_ref_clk; + wire [95:0] gp_out_s; + wire [95:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign gp_out[87:43] = gp_out_s[87:43]; + assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42]; + assign gp_out[41: 0] = gp_out_s[41: 0]; + + assign gp_in_s[95:93] = 3'd0; + assign gp_in_s[92:92] = gp_in_1; + assign gp_in_s[91:88] = gp_in_mio; + assign gp_in_s[87: 0] = gp_in; + + // instantiations + + IBUFDS_GTE2 i_ibufds_gt_ref_clk ( + .CEB (1'd0), + .I (gt_ref_clk_p), + .IB (gt_ref_clk_n), + .O (gt_ref_clk), + .ODIV2 ()); + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( + .dio_t (gpio_t[11:0]), + .dio_i (gpio_o[11:0]), + .dio_o (gpio_i[11:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_in_1 (gp_in_s[63:32]), + .gp_in_2 (gp_in_s[95:64]), + .gp_out_0 (gp_out_s[31:0]), + .gp_out_1 (gp_out_s[63:32]), + .gp_out_2 (gp_out_s[95:64]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .gt_ref_clk (gt_ref_clk), + .gt_rx_0_n (gt_rx_n[0]), + .gt_rx_0_p (gt_rx_p[0]), + .gt_rx_1_n (gt_rx_n[1]), + .gt_rx_1_p (gt_rx_p[1]), + .gt_rx_2_n (gt_rx_n[2]), + .gt_rx_2_p (gt_rx_p[2]), + .gt_rx_3_n (gt_rx_n[3]), + .gt_rx_3_p (gt_rx_p[3]), + .gt_tx_0_n (gt_tx_n[0]), + .gt_tx_0_p (gt_tx_p[0]), + .gt_tx_1_n (gt_tx_n[1]), + .gt_tx_1_p (gt_tx_p[1]), + .gt_tx_2_n (gt_tx_n[2]), + .gt_tx_2_p (gt_tx_p[2]), + .gt_tx_3_n (gt_tx_n[3]), + .gt_tx_3_p (gt_tx_p[3]), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr1/common/ccbrk_bd.tcl b/projects/pzsdr1/common/ccbrk_bd.tcl new file mode 100644 index 000000000..a91b0dafe --- /dev/null +++ b/projects/pzsdr1/common/ccbrk_bd.tcl @@ -0,0 +1,191 @@ + +# lbfmc + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# un-used io (gt) + +set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pzslb_gt +set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt +set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_DATA_SEL_2 {2}] $axi_pzslb_gt +set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_DATA_SEL_3 {3}] $axi_pzslb_gt +set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_pzslb_gt +set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_pzslb_gt +set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_pzslb_gt + +set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0] +set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1] +set util_pzslb_gtlb_2 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_2] +set util_pzslb_gtlb_3 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_3] + +ad_cpu_interconnect 0x44A60000 axi_pzslb_gt +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi + +create_bd_port -dir I gt_ref_clk +create_bd_port -dir I gt_rx_0_p +create_bd_port -dir I gt_rx_0_n +create_bd_port -dir O gt_tx_0_p +create_bd_port -dir O gt_tx_0_n +create_bd_port -dir I gt_rx_1_p +create_bd_port -dir I gt_rx_1_n +create_bd_port -dir O gt_tx_1_p +create_bd_port -dir O gt_tx_1_n +create_bd_port -dir I gt_rx_2_p +create_bd_port -dir I gt_rx_2_n +create_bd_port -dir O gt_tx_2_p +create_bd_port -dir O gt_tx_2_n +create_bd_port -dir I gt_rx_3_p +create_bd_port -dir I gt_rx_3_n +create_bd_port -dir O gt_tx_3_p +create_bd_port -dir O gt_tx_3_n + +ad_connect sys_cpu_clk util_pzslb_gtlb_0/up_clk +ad_connect sys_cpu_resetn util_pzslb_gtlb_0/up_rstn +ad_connect util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_0/rx_p gt_rx_0_p +ad_connect util_pzslb_gtlb_0/rx_n gt_rx_0_n +ad_connect util_pzslb_gtlb_0/tx_p gt_tx_0_p +ad_connect util_pzslb_gtlb_0/tx_n gt_tx_0_n +ad_connect sys_cpu_clk util_pzslb_gtlb_1/up_clk +ad_connect sys_cpu_resetn util_pzslb_gtlb_1/up_rstn +ad_connect util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_1/rx_p gt_rx_1_p +ad_connect util_pzslb_gtlb_1/rx_n gt_rx_1_n +ad_connect util_pzslb_gtlb_1/tx_p gt_tx_1_p +ad_connect util_pzslb_gtlb_1/tx_n gt_tx_1_n +ad_connect sys_cpu_clk util_pzslb_gtlb_2/up_clk +ad_connect sys_cpu_resetn util_pzslb_gtlb_2/up_rstn +ad_connect util_pzslb_gtlb_2/qpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_2/cpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_2/rx_p gt_rx_2_p +ad_connect util_pzslb_gtlb_2/rx_n gt_rx_2_n +ad_connect util_pzslb_gtlb_2/tx_p gt_tx_2_p +ad_connect util_pzslb_gtlb_2/tx_n gt_tx_2_n +ad_connect sys_cpu_clk util_pzslb_gtlb_3/up_clk +ad_connect sys_cpu_resetn util_pzslb_gtlb_3/up_rstn +ad_connect util_pzslb_gtlb_3/qpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_3/cpll_ref_clk gt_ref_clk +ad_connect util_pzslb_gtlb_3/rx_p gt_rx_3_p +ad_connect util_pzslb_gtlb_3/rx_n gt_rx_3_n +ad_connect util_pzslb_gtlb_3/tx_p gt_tx_3_p +ad_connect util_pzslb_gtlb_3/tx_n gt_tx_3_n +ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0 +ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0 +ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0 +ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0 +ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0 +ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0 +ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0 +ad_connect axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0 +ad_connect axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0 +ad_connect axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0 +ad_connect axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0 +ad_connect axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0 +ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0 +ad_connect axi_pzslb_gt/gt_pll_2 util_pzslb_gtlb_2/gt_pll_0 +ad_connect axi_pzslb_gt/gt_rx_2 util_pzslb_gtlb_2/gt_rx_0 +ad_connect axi_pzslb_gt/gt_tx_2 util_pzslb_gtlb_2/gt_tx_0 +ad_connect axi_pzslb_gt/gt_rx_ip_2 util_pzslb_gtlb_2/gt_rx_ip_0 +ad_connect axi_pzslb_gt/gt_tx_ip_2 util_pzslb_gtlb_2/gt_tx_ip_0 +ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_2 util_pzslb_gtlb_2/rx_gt_comma_align_enb_0 +ad_connect axi_pzslb_gt/gt_pll_3 util_pzslb_gtlb_3/gt_pll_0 +ad_connect axi_pzslb_gt/gt_rx_3 util_pzslb_gtlb_3/gt_rx_0 +ad_connect axi_pzslb_gt/gt_tx_3 util_pzslb_gtlb_3/gt_tx_0 +ad_connect axi_pzslb_gt/gt_rx_ip_3 util_pzslb_gtlb_3/gt_rx_ip_0 +ad_connect axi_pzslb_gt/gt_tx_ip_3 util_pzslb_gtlb_3/gt_tx_ip_0 +ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_3 util_pzslb_gtlb_3/rx_gt_comma_align_enb_0 + +# un-used io (regular) + +set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] +set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_0 {0}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_1 {0}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_2 {0}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_5 {0}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg +set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg +set_property -dict [list CONFIG.NUM_OF_IO {7}] $axi_gpreg + +ad_cpu_interconnect 0x41200000 axi_gpreg + +ad_connect util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_0 +ad_connect util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_1 +ad_connect util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_2 +ad_connect util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_3 +ad_connect util_pzslb_gtlb_2/rx_clk axi_gpreg/d_clk_4 +ad_connect util_pzslb_gtlb_2/tx_clk axi_gpreg/d_clk_5 +ad_connect util_pzslb_gtlb_3/rx_clk axi_gpreg/d_clk_6 +ad_connect util_pzslb_gtlb_3/tx_clk axi_gpreg/d_clk_7 + +create_bd_port -dir I -from 31 -to 0 gp_in_0 +create_bd_port -dir I -from 31 -to 0 gp_in_1 +create_bd_port -dir I -from 31 -to 0 gp_in_2 +create_bd_port -dir O -from 31 -to 0 gp_out_0 +create_bd_port -dir O -from 31 -to 0 gp_out_1 +create_bd_port -dir O -from 31 -to 0 gp_out_2 + +ad_connect gp_in_0 axi_gpreg/up_gp_in_0 +ad_connect gp_in_1 axi_gpreg/up_gp_in_1 +ad_connect gp_in_2 axi_gpreg/up_gp_in_2 +ad_connect gp_out_0 axi_gpreg/up_gp_out_0 +ad_connect gp_out_1 axi_gpreg/up_gp_out_1 +ad_connect gp_out_2 axi_gpreg/up_gp_out_2 +ad_connect axi_gpreg/up_gp_in_3 util_pzslb_gtlb_0/up_gp_out +ad_connect axi_gpreg/up_gp_out_3 util_pzslb_gtlb_0/up_gp_in +ad_connect axi_gpreg/up_gp_in_4 util_pzslb_gtlb_1/up_gp_out +ad_connect axi_gpreg/up_gp_out_4 util_pzslb_gtlb_1/up_gp_in +ad_connect axi_gpreg/up_gp_in_5 util_pzslb_gtlb_2/up_gp_out +ad_connect axi_gpreg/up_gp_out_5 util_pzslb_gtlb_2/up_gp_in +ad_connect axi_gpreg/up_gp_in_6 util_pzslb_gtlb_3/up_gp_out +ad_connect axi_gpreg/up_gp_out_6 util_pzslb_gtlb_3/up_gp_in + +## temporary (remove ila indirectly) + +delete_bd_objs [get_bd_cells ila_adc] +delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd] + diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index dbe5a5403..13d3c9715 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -80,6 +80,11 @@ proc adi_project_create {project_name {mode 0}} { set p_board "not-applicable" set sys_zynq 1 } + if [regexp "_pzsdr1$" $project_name] { + set p_device "xc7z020ifbg676-1L" + set p_board "not-applicable" + set sys_zynq 1 + } if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} { return -code error [format "ERROR: This project requires Vivado %s." $REQUIRED_VIVADO_VERSION]