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axi_ad9361/altera- add 10 support

main
Rejeesh Kutty 2017-07-21 10:31:56 -04:00
parent 9b26763e3b
commit bc4526cc8a
8 changed files with 387 additions and 704 deletions
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40
library/axi_ad9361/altera/axi_ad9361_cmos_if.v
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@ -89,6 +89,7 @@ module axi_ad9361_cmos_if #(
input mmcm_rst,
input up_clk,
input up_rstn,
input up_enable,
input up_txnrx,
input [12:0] up_adc_dld,
@ -99,22 +100,35 @@ module axi_ad9361_cmos_if #(
output [79:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
output delay_locked,
// drp interface
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// cmos is not supported on altera platforms yet.
assign tx_clk_out = 'd0;
assign tx_frame_out = 'd0;
assign tx_data_out = 'd0;
assign enable = 'd0;
assign txnrx = 'd0;
assign l_clk = 'd0;
assign adc_valid = 'd0;
assign adc_data = 'd0;
assign adc_status = 'd0;
assign up_adc_drdata = 'd0;
assign up_dac_drdata = 'd0;
assign delay_locked = 'd0;
assign tx_clk_out = 1'd0;
assign tx_frame_out = 1'd0;
assign tx_data_out = 12'd0;
assign enable = 1'd0;
assign txnrx = 1'd0;
assign l_clk = 1'd0;
assign adc_valid = 1'd0;
assign adc_data = 48'd0;
assign adc_status = 1'd0;
assign up_adc_drdata = 65'd0;
assign up_dac_drdata = 80'd0;
assign delay_locked = 1'd0;
assign up_drp_rdata = 32'd0;
assign up_drp_ready = 1'd0;
assign up_drp_locked = 1'd0;
endmodule

88
library/axi_ad9361/altera/axi_ad9361_cmos_out.v
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@ -1,88 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_cmos_out #(
parameter DEVICE_TYPE = 0) (
// data interface
input tx_clk,
input tx_data_p,
input tx_data_n,
output tx_data_out);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// instantiations
generate
if (DEVICE_TYPE == ARRIA10) begin
axi_ad9361_cmos_out_core i_tx_data_oddr (
.clk_export (tx_clk),
.din_export ({tx_data_p, tx_data_n}),
.pad_out_export (tx_data_out));
end
if (DEVICE_TYPE == CYCLONE5) begin
altddio_out #(
.width (1),
.lpm_hint ("UNUSED"))
i_altddio_out (
.outclock (tx_clk),
.datain_h (tx_data_p),
.datain_l (tx_data_n),
.dataout (tx_data_out),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

31
library/axi_ad9361/altera/axi_ad9361_lvds_if.v
View File

@ -468,6 +468,37 @@ module axi_ad9361_lvds_if #(
generate
if (DEVICE_TYPE == ARRIA10) begin
axi_ad9361_lvds_if_10 i_axi_ad9361_lvds_if_10 (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_data_in_n (rx_data_in_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_clk_out_n (tx_clk_out_n),
.tx_frame_out_p (tx_frame_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_data_out_n (tx_data_out_n),
.enable (enable),
.txnrx (txnrx),
.clk (l_clk),
.rx_frame (rx_frame_s),
.rx_data_0 (rx_data_0_s),
.rx_data_1 (rx_data_1_s),
.rx_data_2 (rx_data_2_s),
.rx_data_3 (rx_data_3_s),
.tx_frame (tx_frame),
.tx_data_0 (tx_data_0),
.tx_data_1 (tx_data_1),
.tx_data_2 (tx_data_2),
.tx_data_3 (tx_data_3),
.tx_enable (enable_int_p),
.tx_txnrx (txnrx_int_p),
.locked (locked_s),
.up_clk (up_clk),
.up_rstn (up_rstn));
end
endgenerate

269
library/axi_ad9361/altera/axi_ad9361_lvds_if_10.v Normal file
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@ -0,0 +1,269 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_lvds_if_10 (
// physical interface (receive)
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// ensm control
output enable,
output txnrx,
// clock (common to both receive and transmit)
output clk,
// receive data path interface
output [ 3:0] rx_frame,
output [ 5:0] rx_data_0,
output [ 5:0] rx_data_1,
output [ 5:0] rx_data_2,
output [ 5:0] rx_data_3,
// transmit data path interface
input [ 3:0] tx_frame,
input [ 5:0] tx_data_0,
input [ 5:0] tx_data_1,
input [ 5:0] tx_data_2,
input [ 5:0] tx_data_3,
input tx_enable,
input tx_txnrx,
// locked (status)
output locked,
// delay interface
input up_clk,
input up_rstn);
// internal registers
reg pll_rst = 1'd1;
reg locked_int = 'd0;
// internal signals
wire [27:0] rx_data_s;
wire [ 6:0] rx_data_locked_s;
wire [ 6:0] rx_delay_locked_s;
wire [27:0] tx_data_s;
wire locked_s;
wire alt_lvds_clk;
wire alt_lvds_loaden;
wire [ 7:0] alt_lvds_phase;
// pll reset
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
pll_rst <= 1'b1;
end else begin
pll_rst <= 1'b0;
end
end
assign locked = locked_int;
always @(posedge clk) begin
locked_int <= locked_s & (& rx_data_locked_s) &
(& rx_delay_locked_s);
end
// receive
assign rx_frame[3] = rx_data_s[24];
assign rx_frame[2] = rx_data_s[25];
assign rx_frame[1] = rx_data_s[26];
assign rx_frame[0] = rx_data_s[27];
assign rx_data_3[5] = rx_data_s[20];
assign rx_data_3[4] = rx_data_s[16];
assign rx_data_3[3] = rx_data_s[12];
assign rx_data_3[2] = rx_data_s[ 8];
assign rx_data_3[1] = rx_data_s[ 4];
assign rx_data_3[0] = rx_data_s[ 0];
assign rx_data_2[5] = rx_data_s[21];
assign rx_data_2[4] = rx_data_s[17];
assign rx_data_2[3] = rx_data_s[13];
assign rx_data_2[2] = rx_data_s[ 9];
assign rx_data_2[1] = rx_data_s[ 5];
assign rx_data_2[0] = rx_data_s[ 1];
assign rx_data_1[5] = rx_data_s[22];
assign rx_data_1[4] = rx_data_s[18];
assign rx_data_1[3] = rx_data_s[14];
assign rx_data_1[2] = rx_data_s[10];
assign rx_data_1[1] = rx_data_s[ 6];
assign rx_data_1[0] = rx_data_s[ 2];
assign rx_data_0[5] = rx_data_s[23];
assign rx_data_0[4] = rx_data_s[19];
assign rx_data_0[3] = rx_data_s[15];
assign rx_data_0[2] = rx_data_s[11];
assign rx_data_0[1] = rx_data_s[ 7];
assign rx_data_0[0] = rx_data_s[ 3];
// transmit
assign tx_clk_out_n = 1'd0;
assign tx_frame_out_n = 1'd0;
assign tx_data_out_n = 6'd0;
assign tx_data_s[24] = tx_frame[3];
assign tx_data_s[25] = tx_frame[2];
assign tx_data_s[26] = tx_frame[1];
assign tx_data_s[27] = tx_frame[0];
assign tx_data_s[20] = tx_data_3[5];
assign tx_data_s[16] = tx_data_3[4];
assign tx_data_s[12] = tx_data_3[3];
assign tx_data_s[ 8] = tx_data_3[2];
assign tx_data_s[ 4] = tx_data_3[1];
assign tx_data_s[ 0] = tx_data_3[0];
assign tx_data_s[21] = tx_data_2[5];
assign tx_data_s[17] = tx_data_2[4];
assign tx_data_s[13] = tx_data_2[3];
assign tx_data_s[ 9] = tx_data_2[2];
assign tx_data_s[ 5] = tx_data_2[1];
assign tx_data_s[ 1] = tx_data_2[0];
assign tx_data_s[22] = tx_data_1[5];
assign tx_data_s[18] = tx_data_1[4];
assign tx_data_s[14] = tx_data_1[3];
assign tx_data_s[10] = tx_data_1[2];
assign tx_data_s[ 6] = tx_data_1[1];
assign tx_data_s[ 2] = tx_data_1[0];
assign tx_data_s[23] = tx_data_0[5];
assign tx_data_s[19] = tx_data_0[4];
assign tx_data_s[15] = tx_data_0[3];
assign tx_data_s[11] = tx_data_0[2];
assign tx_data_s[ 7] = tx_data_0[1];
assign tx_data_s[ 3] = tx_data_0[0];
// instantiations
genvar i;
generate
for (i = 0; i < 6; i = i + 1) begin: g_rx_data
axi_ad9361_serdes_in i_rx_data (
.data_in_export (rx_data_in_p[i]),
.clk_export (alt_lvds_clk),
.loaden_export (alt_lvds_loaden),
.div_clk_export (clk),
.hs_phase_export (alt_lvds_phase),
.locked_export (rx_data_locked_s[i]),
.data_s_export (rx_data_s[((i*4)+3):(i*4)]),
.delay_locked_export (rx_delay_locked_s[i]));
end
endgenerate
axi_ad9361_serdes_in i_rx_frame (
.data_in_export (rx_frame_in_p),
.clk_export (alt_lvds_clk),
.loaden_export (alt_lvds_loaden),
.div_clk_export (clk),
.hs_phase_export (alt_lvds_phase),
.locked_export (rx_data_locked_s[6]),
.data_s_export (rx_data_s[27:24]),
.delay_locked_export (rx_delay_locked_s[6]));
generate
for (i = 0; i < 6; i = i + 1) begin: g_tx_data
axi_ad9361_serdes_out i_tx_data (
.data_out_export (tx_data_out_p[i]),
.clk_export (alt_lvds_clk),
.loaden_export (alt_lvds_loaden),
.div_clk_export (clk),
.data_s_export (tx_data_s[((i*4)+3):(i*4)]));
end
endgenerate
axi_ad9361_serdes_out i_tx_frame (
.data_out_export (tx_frame_out_p),
.clk_export (alt_lvds_clk),
.loaden_export (alt_lvds_loaden),
.div_clk_export (clk),
.data_s_export (tx_data_s[27:24]));
axi_ad9361_serdes_out i_tx_clk (
.data_out_export (tx_clk_out_p),
.clk_export (alt_lvds_clk),
.loaden_export (alt_lvds_loaden),
.div_clk_export (clk),
.data_s_export (4'b1010));
axi_ad9361_data_out i_enable (
.ck (clk),
.din ({tx_enable, tx_enable}),
.pad_out (enable));
axi_ad9361_data_out i_txnrx (
.ck (clk),
.din ({tx_txnrx, tx_txnrx}),
.pad_out (txnrx));
axi_ad9361_serdes_clk i_clk (
.rst_reset (pll_rst),
.ref_clk_clk (rx_clk_in_p),
.locked_export (locked_s),
.hs_phase_phout (alt_lvds_phase),
.hs_clk_lvds_clk (alt_lvds_clk),
.loaden_loaden (alt_lvds_loaden),
.ls_clk_clk (clk));
endmodule
// ***************************************************************************
// ***************************************************************************

190
library/axi_ad9361/altera/axi_ad9361_serdes_clk.v
View File

@ -1,190 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module axi_ad9361_serdes_clk #(
// parameters
parameter DEVICE_TYPE = 0) (
// clock and divided clock
input rst,
input clk_in_p,
input clk_in_n,
output clk,
output div_clk,
output out_clk,
output loaden,
output [ 7:0] phase,
// drp interface
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal registers
reg up_drp_sel_int = 'd0;
reg up_drp_rd_int = 'd0;
reg up_drp_wr_int = 'd0;
reg [ 8:0] up_drp_addr_int = 'd0;
reg [31:0] up_drp_wdata_int = 'd0;
reg [31:0] up_drp_rdata_int = 'd0;
reg up_drp_ready_int = 'd0;
reg up_drp_locked_int_m = 'd0;
reg up_drp_locked_int = 'd0;
// internal signals
wire up_drp_reset;
wire [31:0] up_drp_rdata_int_s;
wire up_drp_busy_int_s;
wire up_drp_locked_int_s;
wire loaden_s;
wire clk_s;
// defaults
assign up_drp_reset = ~up_rstn;
assign out_clk = div_clk;
assign up_drp_rdata = up_drp_rdata_int;
assign up_drp_ready = up_drp_ready_int;
assign up_drp_locked = up_drp_locked_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
up_drp_locked_int_m <= 1'd0;
up_drp_locked_int <= 1'd0;
end else begin
if (up_drp_sel_int == 1'b1) begin
if (up_drp_busy_int_s == 1'b0) begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= up_drp_rdata_int_s;
up_drp_ready_int <= 1'b1;
end
end else if (up_drp_sel == 1'b1) begin
up_drp_sel_int <= 1'b1;
up_drp_rd_int <= ~up_drp_wr;
up_drp_wr_int <= up_drp_wr;
up_drp_addr_int <= up_drp_addr[8:0];
up_drp_wdata_int <= up_drp_wdata;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
end else begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
end
up_drp_locked_int_m <= up_drp_locked_int_s;
up_drp_locked_int <= up_drp_locked_int_m;
end
end
generate
if (DEVICE_TYPE == ARRIA10) begin
axi_ad9361_serdes_clk_core i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_phase_phout (phase),
.hs_clk_lvds_clk (clk),
.loaden_loaden (loaden),
.ls_clk_clk (div_clk));
end
if (DEVICE_TYPE == CYCLONE5) begin
assign phase = 8'd0;
axi_ad9361_serdes_clk_pll i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_clk_clk (clk_s),
.loaden_clk (loaden_s),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int[5:0]),
.pll_reconfig_writedata (up_drp_wdata_int));
cyclonev_pll_lvds_output #(
.pll_loaden_enable_disable ("true"),
.pll_lvdsclk_enable_disable ("true"))
i_clk_buf (
.ccout ({loaden_s, clk_s}),
.loaden (loaden),
.lvdsclk (clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

199
library/axi_ad9361/altera/axi_ad9361_serdes_in.v
View File

@ -1,199 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module axi_ad9361_serdes_in #(
// parameters
parameter DEVICE_TYPE = 0,
parameter DATA_WIDTH = 16) (
// reset and clocks
input clk,
input div_clk,
input loaden,
input [ 7:0] phase,
input locked,
// data interface
output [(DATA_WIDTH-1):0] data_s0,
output [(DATA_WIDTH-1):0] data_s1,
output [(DATA_WIDTH-1):0] data_s2,
output [(DATA_WIDTH-1):0] data_s3,
input [(DATA_WIDTH-1):0] data_in_p,
input [(DATA_WIDTH-1):0] data_in_n,
// delay-control interface
output delay_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [(DATA_WIDTH-1):0] delay_locked_s;
wire [(DATA_WIDTH-1):0] data_samples_s[0:3];
wire [ 3:0] data_out_s[0:(DATA_WIDTH-1)];
// assignments
assign delay_locked = & delay_locked_s;
assign data_s3 = data_samples_s[3];
assign data_s2 = data_samples_s[2];
assign data_s1 = data_samples_s[1];
assign data_s0 = data_samples_s[0];
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
assign data_samples_s[0][n] = data_out_s[n][0];
assign data_samples_s[1][n] = data_out_s[n][1];
assign data_samples_s[2][n] = data_out_s[n][2];
assign data_samples_s[3][n] = data_out_s[n][3];
if (DEVICE_TYPE == CYCLONE5) begin
assign delay_locked_s[n] = 1'b1;
altlvds_rx #(
.buffer_implementation ("RAM"),
.cds_mode ("UNUSED"),
.common_rx_tx_pll ("OFF"),
.data_align_rollover (4),
.data_rate ("800.0 Mbps"),
.deserialization_factor (4),
.dpa_initial_phase_value (0),
.dpll_lock_count (0),
.dpll_lock_window (0),
.enable_clock_pin_mode ("UNUSED"),
.enable_dpa_align_to_rising_edge_only ("OFF"),
.enable_dpa_calibration ("ON"),
.enable_dpa_fifo ("UNUSED"),
.enable_dpa_initial_phase_selection ("OFF"),
.enable_dpa_mode ("OFF"),
.enable_dpa_pll_calibration ("OFF"),
.enable_soft_cdr_mode ("OFF"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (50000),
.inclock_phase_shift (0),
.input_data_rate (800),
.intended_device_family ("Cyclone V"),
.lose_lock_on_one_change ("UNUSED"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_serdes_in"),
.lpm_type ("altlvds_rx"),
.number_of_channels (1),
.outclock_resource ("Dual-Regional clock"),
.pll_operation_mode ("NORMAL"),
.pll_self_reset_on_loss_lock ("UNUSED"),
.port_rx_channel_data_align ("PORT_UNUSED"),
.port_rx_data_align ("PORT_UNUSED"),
.refclk_frequency ("20.000000 MHz"),
.registered_data_align_input ("UNUSED"),
.registered_output ("OFF"),
.reset_fifo_at_first_lock ("UNUSED"),
.rx_align_data_reg ("RISING_EDGE"),
.sim_dpa_is_negative_ppm_drift ("OFF"),
.sim_dpa_net_ppm_variation (0),
.sim_dpa_output_clock_phase_shift (0),
.use_coreclock_input ("OFF"),
.use_dpll_rawperror ("OFF"),
.use_external_pll ("ON"),
.use_no_phase_shift ("ON"),
.x_on_bitslip ("ON"),
.clk_src_is_pll ("off"))
i_altlvds_rx (
.rx_enable (loaden),
.rx_in (data_in_p[n]),
.rx_inclock (clk),
.rx_out (data_out_s[n]),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset (1'b0),
.rx_channel_data_align (1'b0),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset (1'b0),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable (1'b1),
.rx_dpll_hold (1'b0),
.rx_dpll_reset (1'b0),
.rx_fifo_reset (1'b0),
.rx_locked (),
.rx_outclock (),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset (1'b0),
.rx_syncclock (1'b0));
end
if (DEVICE_TYPE == ARRIA10) begin
axi_ad9361_serdes_in_core i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.hs_phase_export (phase),
.loaden_export (loaden),
.locked_export (locked),
.data_in_export (data_in_p[n]),
.data_s_export (data_out_s[n]),
.delay_locked_export (delay_locked_s[n]));
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

149
library/axi_ad9361/altera/axi_ad9361_serdes_out.v
View File

@ -1,149 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module axi_ad9361_serdes_out #(
parameter DEVICE_TYPE = 0,
parameter DATA_WIDTH = 16) (
// reset and clocks
input clk,
input div_clk,
input loaden,
// data interface
input [(DATA_WIDTH-1):0] data_s0,
input [(DATA_WIDTH-1):0] data_s1,
input [(DATA_WIDTH-1):0] data_s2,
input [(DATA_WIDTH-1):0] data_s3,
output [(DATA_WIDTH-1):0] data_out_p,
output [(DATA_WIDTH-1):0] data_out_n);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [ 3:0] data_in_s[0:(DATA_WIDTH-1)];
// defaults
assign data_out_n = 'd0;
// instantiations
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
assign data_in_s[n][3] = data_s0[n];
assign data_in_s[n][2] = data_s1[n];
assign data_in_s[n][1] = data_s2[n];
assign data_in_s[n][0] = data_s3[n];
if (DEVICE_TYPE == CYCLONE5) begin
altlvds_tx #(
.center_align_msb ("UNUSED"),
.common_rx_tx_pll ("OFF"),
.coreclock_divide_by (1),
.data_rate ("800.0 Mbps"),
.deserialization_factor (4),
.differential_drive (0),
.enable_clock_pin_mode ("UNUSED"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (50000),
.inclock_phase_shift (0),
.intended_device_family ("Cyclone V"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_serdes_out"),
.lpm_type ("altlvds_tx"),
.multi_clock ("OFF"),
.number_of_channels (1),
.outclock_alignment ("EDGE_ALIGNED"),
.outclock_divide_by (1),
.outclock_duty_cycle (50),
.outclock_multiply_by (1),
.outclock_phase_shift (0),
.outclock_resource ("Dual-Regional clock"),
.output_data_rate (800),
.pll_compensation_mode ("AUTO"),
.pll_self_reset_on_loss_lock ("OFF"),
.preemphasis_setting (0),
.refclk_frequency ("20.000000 MHz"),
.registered_input ("OFF"),
.use_external_pll ("ON"),
.use_no_phase_shift ("ON"),
.vod_setting (0),
.clk_src_is_pll ("off"))
i_altlvds_tx (
.tx_enable (loaden),
.tx_in (data_in_s[n]),
.tx_inclock (clk),
.tx_out (data_out_p[n]),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_data_reset (1'b0),
.tx_locked (),
.tx_outclock (),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
end
if (DEVICE_TYPE == ARRIA10) begin
axi_ad9361_serdes_out_core i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.loaden_export (loaden),
.data_out_export (data_out_p[n]),
.data_s_export (data_in_s[n]));
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

53
library/axi_ad9361/axi_ad9361_hw.tcl
View File

@ -26,12 +26,9 @@ ad_ip_files axi_ad9361 [list\
$ad_hdl_dir/library/common/up_dac_common.v \
$ad_hdl_dir/library/common/up_dac_channel.v \
$ad_hdl_dir/library/common/up_tdd_cntrl.v \
altera/axi_ad9361_serdes_clk.v \
altera/axi_ad9361_serdes_out.v \
altera/axi_ad9361_serdes_in.v \
altera/axi_ad9361_cmos_out.v \
altera/axi_ad9361_lvds_if.v \
altera/axi_ad9361_lvds_if_10.v \
altera/axi_ad9361_lvds_if_c5.v \
altera/axi_ad9361_lvds_if.v \
altera/axi_ad9361_cmos_if.v \
axi_ad9361_rx_pnmon.v \
axi_ad9361_rx_channel.v \
@ -171,33 +168,31 @@ proc axi_ad9361_elab {} {
if {$m_device_family eq "Arria 10"} {
add_hdl_instance axi_ad9361_serdes_clk_core alt_serdes
set_instance_parameter_value axi_ad9361_serdes_clk_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value axi_ad9361_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_clk alt_serdes
set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK}
set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_in_core alt_serdes
set_instance_parameter_value axi_ad9361_serdes_in_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_in_core {MODE} {IN}
set_instance_parameter_value axi_ad9361_serdes_in_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_in_core {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_in_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_in alt_serdes
set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_in {MODE} {IN}
set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_out_core alt_serdes
set_instance_parameter_value axi_ad9361_serdes_out_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_out_core {MODE} {OUT}
set_instance_parameter_value axi_ad9361_serdes_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_out_core {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_out_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_out alt_serdes
set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT}
set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_out {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_cmos_out_core alt_serdes
set_instance_parameter_value axi_ad9361_cmos_out_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_cmos_out_core {MODE} {OUT}
set_instance_parameter_value axi_ad9361_cmos_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_cmos_out_core {SERDES_FACTOR} {2}
set_instance_parameter_value axi_ad9361_cmos_out_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_data_out altera_gpio
set_instance_parameter_value axi_ad9361_data_out {PIN_TYPE_GUI} {Output}
set_instance_parameter_value axi_ad9361_data_out {SIZE} {1}
set_instance_parameter_value axi_ad9361_data_out {gui_io_reg_mode} {DDIO}
}
add_interface device_if conduit end