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axi_ad9739a: Update core to the new DRP interface

main
Istvan Csomortani 2016-09-21 15:23:08 +03:00
parent 781702c1b9
commit bae839acd4
1 changed files with 13 additions and 10 deletions
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9
library/axi_ad9739a/axi_ad9739a_if.v
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@ -143,13 +143,14 @@ module axi_ad9739a_if (
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES_OR_DDR_N(1),
.DDR_OR_SDR_N(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (DEVICE_TYPE))
i_serdes_out_data_a (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_s0 (dac_data_00[15:2]),
.data_s1 (dac_data_02[15:2]),
.data_s2 (dac_data_04[15:2]),
@ -164,13 +165,14 @@ module axi_ad9739a_if (
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES_OR_DDR_N(1),
.DDR_OR_SDR_N(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (DEVICE_TYPE))
i_serdes_out_data_b (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_s0 (dac_data_01[15:2]),
.data_s1 (dac_data_03[15:2]),
.data_s2 (dac_data_05[15:2]),
@ -185,13 +187,14 @@ module axi_ad9739a_if (
// dac clock output serdes & buffer
ad_serdes_out #(
.SERDES_OR_DDR_N(1),
.DDR_OR_SDR_N(1),
.DATA_WIDTH(1),
.DEVICE_TYPE (DEVICE_TYPE))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),