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axi_streaming_dma_rx_fifo: fix period_count clock and TLAST 

The period_count should be updated once per clock cycle. This is not
enforced with the current implementation, which probably leads to
period_count being decremented on both m_axis_aclk edges.

A problem observed due to this is that the m_axis_tlast output is not
asserted or is asserted for a too short time for the consumer to
detect it.

Fix by letting the decrement (and thus the m_axis_tlast toggling)
happen only on the rising edge of the m_axis_aclk clock.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
main
Luca Ceresoli 2017-12-05 12:47:52 +01:00 committed by István Csomortáni
parent 386febaa7e
commit ba24909a25
1 changed files with 10 additions and 8 deletions
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18
library/common/axi_streaming_dma_rx_fifo.vhd
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@ -100,14 +100,16 @@ begin
period_counter: process(m_axis_aclk) is
begin
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and m_axis_tready = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
if rising_edge(m_axis_aclk) then
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and m_axis_tready = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end if;