Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
acozma
commit
b9ca616150
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -41,7 +41,7 @@
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module axi_ad9671 (
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// jesd interface
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// jesd interface
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// rx_clk is (line-rate/40)
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rx_clk,
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@ -56,6 +56,8 @@ module axi_ad9671 (
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adc_data,
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adc_dovf,
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adc_dunf,
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adc_sync_in,
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adc_sync_out,
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adc_raddr_in,
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adc_raddr_out,
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@ -89,7 +91,7 @@ module axi_ad9671 (
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parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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// jesd interface
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// jesd interface
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// rx_clk is the jesd clock (ref_clk/2)
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input rx_clk;
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@ -104,6 +106,8 @@ module axi_ad9671 (
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output [127:0] adc_data;
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input adc_dovf;
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input adc_dunf;
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input adc_sync_in;
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output adc_sync_out;
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input [ 3:0] adc_raddr_in;
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output [ 3:0] adc_raddr_out;
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@ -149,6 +153,7 @@ module axi_ad9671 (
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// internal signals
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wire adc_status_s;
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wire adc_sync_status_s;
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wire adc_valid_s;
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wire [ 15:0] adc_data_s[7:0];
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wire [ 7:0] adc_or_s;
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@ -163,6 +168,8 @@ module axi_ad9671 (
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wire [ 31:0] up_rdata_s[8:0];
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wire up_rack_s[8:0];
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wire up_wack_s[8:0];
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wire [ 31:0] adc_start_code;
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wire adc_sync;
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// signal name changes
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@ -194,7 +201,10 @@ module axi_ad9671 (
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// main (device interface)
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axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N), .PCORE_ID(PCORE_ID)) i_if (
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axi_ad9671_if #(
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.PCORE_4L_2L_N(PCORE_4L_2L_N),
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.PCORE_ID(PCORE_ID)
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) i_if (
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.rx_clk (rx_clk),
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.rx_data (rx_data),
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.rx_data_sof (rx_data_sof),
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@ -217,6 +227,11 @@ module axi_ad9671 (
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.adc_or_g (adc_or_s[6]),
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.adc_data_h (adc_data_s[7]),
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.adc_or_h (adc_or_s[7]),
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.adc_start_code (adc_start_code),
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.adc_sync (adc_sync),
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.adc_sync_in (adc_sync_in),
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.adc_sync_out (adc_sync_out),
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.adc_sync_status (adc_sync_status_s),
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.adc_status (adc_status_s),
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.adc_raddr_in(adc_raddr_in),
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.adc_raddr_out(adc_raddr_out));
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@ -253,13 +268,18 @@ module axi_ad9671 (
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// common processor control
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up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
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up_adc_common #(
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.PCORE_ID(PCORE_ID)
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) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_start_code (adc_start_code),
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.adc_sync (adc_sync),
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.adc_sync_status (adc_sync_status_s),
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.adc_status (adc_status_s),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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@ -70,6 +70,11 @@ module axi_ad9671_if (
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adc_or_g,
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adc_data_h,
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adc_or_h,
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adc_start_code,
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adc_sync_in,
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adc_sync_out,
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adc_sync,
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adc_sync_status,
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adc_status,
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adc_raddr_in,
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adc_raddr_out);
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@ -107,6 +112,11 @@ module axi_ad9671_if (
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output adc_or_g;
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output [ 15:0] adc_data_h;
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output adc_or_h;
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input [ 31:0] adc_start_code;
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input adc_sync_in;
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output adc_sync_out;
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input adc_sync;
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output adc_sync_status;
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output adc_status;
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input [ 3:0] adc_raddr_in;
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output [ 3:0] adc_raddr_out;
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@ -124,13 +134,14 @@ module axi_ad9671_if (
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wire [ 15:0] adc_data_g_s;
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wire [ 15:0] adc_data_h_s;
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wire [ 3:0] adc_raddr_s;
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wire adc_sync_s;
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// internal registers
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reg int_valid = 'd0;
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reg [127:0] int_data = 'd0;
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reg adc_status = 'd0;
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reg adc_start = 'd0;
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reg adc_sync_status = 'd0;
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reg [ 3:0] adc_waddr = 'd0;
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reg [ 3:0] adc_raddr_out = 'd0;
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@ -146,7 +157,8 @@ module axi_ad9671_if (
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// adc clock & valid
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assign adc_clk = rx_clk;
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assign adc_valid = int_valid & adc_start;
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assign adc_valid = int_valid;
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assign adc_sync_out = adc_sync;
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assign adc_or_a = 'd0;
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assign adc_or_b = 'd0;
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@ -170,9 +182,9 @@ module axi_ad9671_if (
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adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
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assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
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assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in;
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always @(posedge rx_clk)
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begin
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always @(posedge rx_clk) begin
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adc_data_a <= adc_rdata[ 15: 0];
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adc_data_b <= adc_rdata[ 31: 16];
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adc_data_c <= adc_rdata[ 47: 32];
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@ -185,17 +197,21 @@ module axi_ad9671_if (
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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adc_start <= 1'b0;
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end
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else begin
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if (int_valid == 1'b1 && adc_data_a_s == 16'hbeef) begin
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adc_start <= 1'b1;
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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adc_sync_status <= 1'b0;
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end else begin
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if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
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adc_sync_status <= 1'b0;
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end else if(adc_sync_s == 1'b1) begin
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adc_sync_status <= 1'b1;
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end
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if (int_valid == 1'b1 && adc_start == 1'b1) begin
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adc_waddr <= adc_waddr + 1;
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adc_raddr_out <= adc_raddr_out + 1;
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if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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end else if (int_valid == 1'b1) begin
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adc_waddr <= adc_waddr + 1;
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adc_raddr_out <= adc_raddr_out + 1;
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end
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end
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end
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@ -0,0 +1,24 @@
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if { [get_clocks -quiet -of_objects [get_ports s_axi_aclk]] != ""} {
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
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}
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if { [get_clocks -quiet -of_objects [get_ports m_dest_axi_aclk]] != ""} {
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
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}
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if { [get_clocks -quiet -of_objects [get_ports m_src_axi_aclk]] != ""} {
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_src_axi_aclk]]
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}
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if { [get_clocks -quiet -of_objects [get_ports s_axis_aclk]] != ""} {
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axis_aclk]]
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}
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if { [get_clocks -quiet -of_objects [get_ports m_axis_aclk]] != ""} {
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_aclk]]
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}
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if { [get_clocks -quiet -of_objects [get_ports fifo_rd_clk]] != ""} {
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_rd_clk]]
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}
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@ -1,4 +0,0 @@
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@ -29,11 +29,11 @@ adi_ip_files axi_dmac [list \
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"response_generator.v" \
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"axi_dmac.v" \
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"axi_repack.v" \
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"axi_dmac_constr.xdc" ]
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"axi_dmac_constr.tcl" ]
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adi_ip_properties axi_dmac
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adi_ip_constraints axi_dmac [list \
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"axi_dmac_constr.xdc" ]
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"axi_dmac_constr.tcl" ]
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set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
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[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
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@ -312,8 +312,11 @@ module axi_jesd_gt (
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wire drp_ready_gt_s[15:0];
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wire [ 7:0] drp_rx_rate_gt_s[15:0];
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wire [287:0] tx_gt_data_extn_zero_s;
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wire [ 35:0] tx_gt_charisk_extn_zero_s;
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wire [287:0] tx_gt_data_extn_s;
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wire [ 35:0] tx_gt_charisk_extn_s;
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wire [287:0] tx_gt_data_mux_s;
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wire [ 35:0] tx_gt_charisk_mux_s;
|
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wire qpll_locked_0_s;
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wire qpll_locked_1_s;
|
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wire [ 7:0] qpll_locked_s;
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@ -430,7 +433,9 @@ module axi_jesd_gt (
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assign tx_ip_data = tx_data;
|
||||
|
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assign tx_gt_data_extn_zero_s = 288'd0;
|
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assign tx_gt_charisk_extn_zero_s = 36'd0;
|
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assign tx_gt_data_extn_s = {tx_gt_data_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*32)-1):0], tx_gt_data};
|
||||
assign tx_gt_charisk_extn_s = {tx_gt_charisk_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*4)-1):0], tx_gt_charisk};
|
||||
|
||||
assign tx_gt_data_mux_s[((8*32)+31):(8*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_8*32)+31):(PCORE_TX_LANE_SEL_8*32)];
|
||||
assign tx_gt_data_mux_s[((7*32)+31):(7*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_7*32)+31):(PCORE_TX_LANE_SEL_7*32)];
|
||||
|
|
@ -441,6 +446,15 @@ module axi_jesd_gt (
|
|||
assign tx_gt_data_mux_s[((2*32)+31):(2*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_2*32)+31):(PCORE_TX_LANE_SEL_2*32)];
|
||||
assign tx_gt_data_mux_s[((1*32)+31):(1*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_1*32)+31):(PCORE_TX_LANE_SEL_1*32)];
|
||||
assign tx_gt_data_mux_s[((0*32)+31):(0*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_0*32)+31):(PCORE_TX_LANE_SEL_0*32)];
|
||||
assign tx_gt_charisk_mux_s[((8*4)+3):(8*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_8*4)+3):(PCORE_TX_LANE_SEL_8*4)];
|
||||
assign tx_gt_charisk_mux_s[((7*4)+3):(7*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_7*4)+3):(PCORE_TX_LANE_SEL_7*4)];
|
||||
assign tx_gt_charisk_mux_s[((6*4)+3):(6*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_6*4)+3):(PCORE_TX_LANE_SEL_6*4)];
|
||||
assign tx_gt_charisk_mux_s[((5*4)+3):(5*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_5*4)+3):(PCORE_TX_LANE_SEL_5*4)];
|
||||
assign tx_gt_charisk_mux_s[((4*4)+3):(4*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_4*4)+3):(PCORE_TX_LANE_SEL_4*4)];
|
||||
assign tx_gt_charisk_mux_s[((3*4)+3):(3*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_3*4)+3):(PCORE_TX_LANE_SEL_3*4)];
|
||||
assign tx_gt_charisk_mux_s[((2*4)+3):(2*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_2*4)+3):(PCORE_TX_LANE_SEL_2*4)];
|
||||
assign tx_gt_charisk_mux_s[((1*4)+3):(1*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_1*4)+3):(PCORE_TX_LANE_SEL_1*4)];
|
||||
assign tx_gt_charisk_mux_s[((0*4)+3):(0*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_0*4)+3):(PCORE_TX_LANE_SEL_0*4)];
|
||||
|
||||
// clock buffers
|
||||
|
||||
|
|
@ -573,7 +587,7 @@ module axi_jesd_gt (
|
|||
.tx_rst_done (tx_rst_done_s[n]),
|
||||
.tx_pll_locked (tx_pll_locked_s[n]),
|
||||
.tx_clk (tx_clk),
|
||||
.tx_charisk (tx_gt_charisk[n*4+3:n*4]),
|
||||
.tx_charisk (tx_gt_charisk_mux_s[n*4+3:n*4]),
|
||||
.tx_data (tx_gt_data_mux_s[n*32+31:n*32]),
|
||||
.drp_clk (drp_clk),
|
||||
.drp_sel (drp_sel_s),
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@ if {$sys_zynq == 0} {
|
|||
connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_data] [get_bd_pins axi_ad9467_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_dovf] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow]
|
||||
|
||||
connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -156,8 +156,8 @@ if {$sys_zynq == 1 } {
|
|||
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
|
||||
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
|
||||
|
||||
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
|
||||
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
|
||||
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10]
|
||||
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In9]
|
||||
}
|
||||
|
||||
if {$sys_zynq == 1 } {
|
||||
|
|
@ -210,7 +210,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_fifo
|
|||
connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo/dma_wvalid] [get_bd_pins axi_ad9625_dma/s_axis_valid]
|
||||
connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready]
|
||||
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data]
|
||||
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -101,7 +101,6 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
|
|||
|
||||
set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect
|
||||
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
|
||||
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
|
||||
|
||||
delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
|
||||
delete_bd_objs [get_bd_ports unc_int2]
|
||||
|
|
@ -120,8 +119,8 @@ connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins
|
|||
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
|
||||
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
|
||||
|
||||
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
|
||||
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
|
||||
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10]
|
||||
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In9]
|
||||
|
||||
# connections (gt)
|
||||
|
||||
|
|
@ -193,7 +192,7 @@ connect_bd_net -net axi_ad9625_dma_adc_dsync [get_bd_pins axi_ad9625_dm
|
|||
connect_bd_net -net axi_ad9625_dma_adc_ddata [get_bd_pins axi_ad9625_dma/fifo_wr_din] [get_bd_ports dma_data]
|
||||
|
||||
connect_bd_net -net axi_ad9625_dma_adc_dovf [get_bd_pins axi_ad9625_0_core/adc_dovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ connect_bd_net -net axi_ad9671_core_adc_dwr [get_bd_ports dma_wr]
|
|||
connect_bd_net -net axi_ad9671_core_adc_dsync [get_bd_ports dma_sync] [get_bd_pins axi_ad9671_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_ad9671_core_adc_ddata [get_bd_ports dma_data] [get_bd_pins axi_ad9671_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dovf [get_bd_pins axi_ad9671_core/adc_dovf] [get_bd_pins axi_ad9671_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -37,14 +37,3 @@ set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_ad95
|
|||
|
||||
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
|
||||
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_ad9671_gt_rx_clk]
|
||||
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
|
||||
|
||||
set_clock_groups -asynchronous -group {rx_div_clk}
|
||||
set_clock_groups -asynchronous -group {fmc_dma_clk}
|
||||
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core
|
|||
connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -79,7 +79,6 @@ module system_top (
|
|||
gpio_led,
|
||||
gpio_sw,
|
||||
|
||||
iic_rstn,
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
|
|
@ -129,7 +128,6 @@ module system_top (
|
|||
inout [ 7:0] gpio_led;
|
||||
inout [ 8:0] gpio_sw;
|
||||
|
||||
output iic_rstn;
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
|
|
@ -173,7 +171,6 @@ module system_top (
|
|||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.iic_rstn (iic_rstn),
|
||||
.mdio_mdc (mdio_mdc),
|
||||
.mdio_mdio_io (mdio_mdio),
|
||||
.phy_clk_clk_n (phy_clk_n),
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@ set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface
|
|||
set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
|
||||
set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd]
|
||||
|
||||
set iic_rstn [create_bd_port -dir O iic_rstn]
|
||||
set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main]
|
||||
|
||||
set uart_sin [create_bd_port -dir I uart_sin]
|
||||
|
|
@ -428,7 +427,6 @@ connect_bd_intf_net -intf_net gpio_led [get_bd_intf_ports gpio_led] [get_bd_in
|
|||
connect_bd_intf_net -intf_net iic_main [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic]
|
||||
connect_bd_net -net uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
|
||||
connect_bd_net -net uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
|
||||
connect_bd_net -net iic_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo]
|
||||
|
||||
# hdmi
|
||||
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports gpio_le
|
|||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN AP10 IOSTANDARD LVCMOS18} [get_ports iic_rstn]
|
||||
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda]
|
||||
|
||||
|
|
|
|||
|
|
@ -455,7 +455,7 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S
|
|||
connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] $sys_200m_clk_source
|
||||
connect_bd_net -net sys_100m_reset [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ connect_bd_net -net axi_ad9250_adc_dovf [get_bd_pins axi_ad9250_core/a
|
|||
connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports adc_dwr]
|
||||
connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports adc_dsync]
|
||||
connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports adc_ddata]
|
||||
connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
connect_bd_net -net axi_ad9250_adc_clk [get_bd_ports adc_clk]
|
||||
|
||||
|
|
@ -199,7 +199,7 @@ connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122_core/d
|
|||
connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_drd]
|
||||
connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_ddata]
|
||||
connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
|
||||
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
|
||||
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12]
|
||||
|
||||
connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_ports dac_clk]
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -79,7 +79,6 @@ module system_top (
|
|||
gpio_led,
|
||||
gpio_sw,
|
||||
|
||||
iic_rstn,
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
|
|
@ -165,7 +164,6 @@ module system_top (
|
|||
inout [ 7:0] gpio_led;
|
||||
inout [ 8:0] gpio_sw;
|
||||
|
||||
output iic_rstn;
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
|
|
@ -491,7 +489,6 @@ module system_top (
|
|||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.iic_rstn (iic_rstn),
|
||||
.mdio_mdc (mdio_mdc),
|
||||
.mdio_mdio_io (mdio_mdio),
|
||||
.phy_clk_clk_n (phy_clk_n),
|
||||
|
|
|
|||
|
|
@ -3,55 +3,3 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
|||
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
|
||||
source ../common/daq2_bd.tcl
|
||||
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
|
||||
|
||||
p_plddr3_fifo [current_bd_instance .] plddr3_fifo 128
|
||||
|
||||
set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3]
|
||||
set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk]
|
||||
|
||||
connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3]
|
||||
connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk]
|
||||
|
||||
delete_bd_objs [get_bd_nets axi_ad9680_adc_clk]
|
||||
delete_bd_objs [get_bd_nets axi_ad9680_adc_dwr]
|
||||
delete_bd_objs [get_bd_nets axi_ad9680_adc_ddata]
|
||||
delete_bd_objs [get_bd_nets axi_ad9680_adc_dsync]
|
||||
delete_bd_objs [get_bd_nets axi_ad9680_adc_dovf]
|
||||
|
||||
connect_bd_net -net [get_bd_nets axi_daq2_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst]
|
||||
connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn]
|
||||
connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req]
|
||||
|
||||
connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk]
|
||||
connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf]
|
||||
connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr]
|
||||
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata]
|
||||
|
||||
connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk]
|
||||
connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/fifo_wr_en]
|
||||
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9680_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync]
|
||||
|
||||
connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk]
|
||||
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
|
||||
|
||||
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_dma_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon
|
||||
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon
|
||||
|
||||
connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins ila_dma_mon/clk]
|
||||
connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins ila_dma_mon/probe0]
|
||||
connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins ila_dma_mon/probe1]
|
||||
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins ila_dma_mon/probe2]
|
||||
|
||||
|
||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr
|
||||
|
||||
|
|
|
|||
|
|
@ -18,14 +18,14 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
|
|||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P
|
||||
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N
|
||||
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P
|
||||
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N
|
||||
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P
|
||||
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N
|
||||
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P
|
||||
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N
|
||||
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0])
|
||||
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0])
|
||||
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3])
|
||||
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3])
|
||||
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1])
|
||||
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1])
|
||||
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2])
|
||||
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2])
|
||||
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
|
||||
|
|
@ -58,19 +58,4 @@ create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
|
|||
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk]
|
||||
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
|
||||
create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk]
|
||||
create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0]
|
||||
|
||||
set_clock_groups -asynchronous -group {tx_div_clk}
|
||||
set_clock_groups -asynchronous -group {rx_div_clk}
|
||||
set_clock_groups -asynchronous -group {fmc_dma_clk}
|
||||
set_clock_groups -asynchronous -group {pl_ddr_clk}
|
||||
set_clock_groups -asynchronous -group {pl_dma_clk}
|
||||
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]
|
||||
|
|
|
|||
|
|
@ -12,6 +12,9 @@ adi_project_files daq2_zc706 [list \
|
|||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
|
||||
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
|
||||
|
||||
adi_project_run daq2_zc706
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -299,7 +299,7 @@ if {$sys_zynq == 0} {
|
|||
connect_bd_net -net axi_ad9152_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9152_dma/fifo_rd_en]
|
||||
connect_bd_net -net axi_ad9152_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9152_dma/fifo_rd_dout]
|
||||
connect_bd_net -net axi_ad9152_dac_dunf [get_bd_pins axi_ad9152_core/dac_dunf] [get_bd_pins axi_ad9152_dma/fifo_rd_underflow]
|
||||
connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In3]
|
||||
connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In12]
|
||||
|
||||
# connections (adc)
|
||||
|
||||
|
|
@ -341,7 +341,7 @@ if {$sys_zynq == 1} {
|
|||
connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
|
||||
connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
|
||||
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
|
||||
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
}
|
||||
|
||||
# dac/adc clocks
|
||||
|
|
|
|||
|
|
@ -216,8 +216,8 @@ connect_bd_net -net axi_ad9250_1_dma_data [get_bd_pins axi_ad9250_1_dm
|
|||
|
||||
connect_bd_net -net axi_ad9250_0_adc_dovf [get_bd_pins axi_ad9250_0_core/adc_dovf] [get_bd_pins axi_ad9250_0_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9250_1_adc_dovf [get_bd_pins axi_ad9250_1_core/adc_dovf] [get_bd_pins axi_ad9250_1_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In3]
|
||||
connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In12]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ if {$sys_zynq == 0} {
|
|||
|
||||
connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_dma_rd]
|
||||
connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_dma_rdata]
|
||||
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
|
||||
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12]
|
||||
|
||||
# connections (adc)
|
||||
|
||||
|
|
@ -160,7 +160,7 @@ if {$sys_zynq == 0} {
|
|||
connect_bd_net -net axi_ad9643_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9643_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
|
||||
# interconnect (cpu)
|
||||
|
|
|
|||
|
|
@ -251,8 +251,8 @@ if {$sys_zynq == 0} {
|
|||
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In5]
|
||||
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In6]
|
||||
} else {
|
||||
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3]
|
||||
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12]
|
||||
}
|
||||
|
||||
# interconnect (cpu)
|
||||
|
|
|
|||
|
|
@ -129,8 +129,7 @@ if {$sys_zynq == 0} {
|
|||
set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_intc
|
||||
} else {
|
||||
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
|
||||
set_property -dict [list CONFIG.NUM_PORTS {6}] $sys_concat_intc
|
||||
}
|
||||
}
|
||||
|
||||
if {$sys_zynq == 1} {
|
||||
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
|
||||
|
|
@ -277,9 +276,9 @@ connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0
|
|||
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
|
||||
connect_bd_net -net axi_ad9361_fifo_valid [get_bd_pins util_dac_unpack_0/fifo_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
|
||||
connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
|
||||
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3]
|
||||
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@ connect_bd_net -net axi_ad9652_dma_dwr [get_bd_pins sys_wfifo/s_wr]
|
|||
connect_bd_net -net axi_ad9652_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9652_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_ad9652_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9652_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9652_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9652_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
|
|||
|
|
@ -131,25 +131,25 @@ connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_u
|
|||
connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o]
|
||||
connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
|
||||
connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
|
||||
connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12]
|
||||
|
||||
# connections (gt)
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref]
|
||||
connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref]
|
||||
|
||||
# connections (adc)
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk_g]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk]
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset]
|
||||
|
|
@ -193,11 +193,15 @@ connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core
|
|||
connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en]
|
||||
connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data]
|
||||
connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
|
||||
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In13]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_0/adc_raddr_out]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_3/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_0/adc_sync_out]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_1/adc_sync_in]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_2/adc_sync_in]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_3/adc_sync_in]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
@ -217,14 +221,14 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sy
|
|||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
|
|
@ -233,14 +237,14 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESET
|
|||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
|
||||
|
||||
# interconnect (gt es)
|
||||
|
||||
|
|
@ -266,7 +270,7 @@ connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
|
|||
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
|
||||
|
|
@ -275,7 +279,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk]
|
|||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
|
||||
|
||||
# ila
|
||||
|
||||
|
|
|
|||
|
|
@ -83,15 +83,3 @@ set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data
|
|||
|
||||
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
|
||||
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk]
|
||||
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
|
||||
create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3]
|
||||
|
||||
set_clock_groups -asynchronous -group {rx_div_clk}
|
||||
set_clock_groups -asynchronous -group {fmc_dma_clk}
|
||||
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]
|
||||
|
|
|
|||
Loading…
Reference in New Issue