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adrv9371: update adcfifo/dacfifo

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Laszlo Nagy 2019-01-22 13:19:09 +00:00 committed by Laszlo Nagy
parent 3183fbf226
commit b98eb28dca
7 changed files with 11 additions and 15 deletions
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3
projects/adrv9371x/a10gx/system_qsys.tcl
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@ -1,8 +1,5 @@
set dac_fifo_name avl_ad9371_tx_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source $ad_hdl_dir/projects/common/altera/dacfifo_qsys.tcl

3
projects/adrv9371x/a10soc/system_qsys.tcl
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@ -1,8 +1,5 @@
set dac_fifo_name avl_ad9371_tx_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl

6
projects/adrv9371x/common/adrv9371x_bd.tcl
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@ -23,6 +23,10 @@ set RX_OS_SAMPLE_WIDTH 16 ; # N/NP
set RX_OS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
set dac_fifo_name axi_ad9371_dacfifo
set dac_data_width [expr 32*$TX_NUM_OF_LANES]
set dac_dma_data_width 128
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# ad9371
@ -71,6 +75,8 @@ ad_ip_parameter axi_ad9371_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
# adc peripherals
ad_ip_instance axi_clkgen axi_ad9371_rx_clkgen

5
projects/adrv9371x/common/adrv9371x_qsys.tcl
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@ -1,3 +1,6 @@
set dac_fifo_name avl_ad9371_tx_fifo
set dac_data_width 128
set dac_dma_data_width 128
# ad9371_tx JESD204
@ -116,6 +119,8 @@ add_connection axi_ad9371_rx_os_cpack.if_fifo_wr_overflow axi_ad9371.if_adc_os_d
# dac fifo
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
add_interface tx_fifo_bypass conduit end
set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9371_tx_fifo.if_bypass

3
projects/adrv9371x/kcu105/system_bd.tcl
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@ -1,9 +1,6 @@
## FIFO depth is 8Mb - 500k samples
set dac_fifo_name axi_ad9371_dacfifo
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~68%

3
projects/adrv9371x/zc706/system_bd.tcl
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@ -1,8 +1,5 @@
set dac_fifo_name axi_ad9371_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl

3
projects/adrv9371x/zcu102/system_bd.tcl
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@ -1,9 +1,6 @@
## FIFO depth is 16Mb - 1M samples
set dac_fifo_name axi_ad9371_dacfifo
set dac_fifo_address_width 17
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~51%